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drm/i915: Fix FBC1 plane checks for gen2 

On gen2 and gen3 chipsets FBC is supported only on plane A. Fix (and
simplify) the plane checks in intel_update_fbc() accordingly.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2013-11-28 17:29:58 +02:00 committed by Daniel Vetter
parent 82f344967c
commit c5a44aa012
1 changed files with 3 additions and 3 deletions
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6
drivers/gpu/drm/i915/intel_pm.c
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@ -537,10 +537,10 @@ void intel_update_fbc(struct drm_device *dev)
DRM_DEBUG_KMS("mode too large for compression, disabling\n"); DRM_DEBUG_KMS("mode too large for compression, disabling\n");
goto out_disable; goto out_disable;
} }
if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) && if ((INTEL_INFO(dev)->gen < 4 || IS_HASWELL(dev)) &&
intel_crtc->plane != 0) { intel_crtc->plane != PLANE_A) {
if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
DRM_DEBUG_KMS("plane not 0, disabling compression\n"); DRM_DEBUG_KMS("plane not A, disabling compression\n");
goto out_disable; goto out_disable;
} }