i40e/i40evf: Add set_fc and init of FC settings
Add function set_fc to set the requested FC mode. This patch also adds the init of FC setting to get_link_info and replaces the init code to set FC off by default in main. Also adds i40e_set_phy_config to support this. Change-ID: I7b25bbaec81f15777137ab324a095f916e44351d Signed-off-by: Catherine Sullivan <catherine.sullivan@intel.com> Tested-by: Jim Young <jamesx.m.young@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
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@ -1082,6 +1082,118 @@ i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
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return status;
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}
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/**
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* i40e_aq_set_phy_config
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* @hw: pointer to the hw struct
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* @config: structure with PHY configuration to be set
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* @cmd_details: pointer to command details structure or NULL
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*
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* Set the various PHY configuration parameters
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* supported on the Port.One or more of the Set PHY config parameters may be
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* ignored in an MFP mode as the PF may not have the privilege to set some
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* of the PHY Config parameters. This status will be indicated by the
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* command response.
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**/
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enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
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struct i40e_aq_set_phy_config *config,
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struct i40e_asq_cmd_details *cmd_details)
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{
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struct i40e_aq_desc desc;
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struct i40e_aq_set_phy_config *cmd =
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(struct i40e_aq_set_phy_config *)&desc.params.raw;
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enum i40e_status_code status;
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if (!config)
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return I40E_ERR_PARAM;
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i40e_fill_default_direct_cmd_desc(&desc,
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i40e_aqc_opc_set_phy_config);
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*cmd = *config;
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status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
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return status;
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}
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/**
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* i40e_set_fc
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* @hw: pointer to the hw struct
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*
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* Set the requested flow control mode using set_phy_config.
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**/
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enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
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bool atomic_restart)
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{
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enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
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struct i40e_aq_get_phy_abilities_resp abilities;
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struct i40e_aq_set_phy_config config;
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enum i40e_status_code status;
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u8 pause_mask = 0x0;
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*aq_failures = 0x0;
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switch (fc_mode) {
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case I40E_FC_FULL:
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pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
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pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
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break;
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case I40E_FC_RX_PAUSE:
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pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
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break;
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case I40E_FC_TX_PAUSE:
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pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
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break;
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default:
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break;
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}
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/* Get the current phy config */
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status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
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NULL);
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if (status) {
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*aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
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return status;
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}
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memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
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/* clear the old pause settings */
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config.abilities = abilities.abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
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~(I40E_AQ_PHY_FLAG_PAUSE_RX);
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/* set the new abilities */
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config.abilities |= pause_mask;
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/* If the abilities have changed, then set the new config */
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if (config.abilities != abilities.abilities) {
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/* Auto restart link so settings take effect */
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if (atomic_restart)
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config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
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/* Copy over all the old settings */
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config.phy_type = abilities.phy_type;
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config.link_speed = abilities.link_speed;
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config.eee_capability = abilities.eee_capability;
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config.eeer = abilities.eeer_val;
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config.low_power_ctrl = abilities.d3_lpan;
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status = i40e_aq_set_phy_config(hw, &config, NULL);
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if (status)
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*aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
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}
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/* Update the link info */
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status = i40e_update_link_info(hw, true);
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if (status) {
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/* Wait a little bit (on 40G cards it sometimes takes a really
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* long time for link to come back from the atomic reset)
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* and try once more
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*/
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msleep(1000);
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status = i40e_update_link_info(hw, true);
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}
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if (status)
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*aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
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return status;
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}
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/**
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* i40e_aq_clear_pxe_mode
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* @hw: pointer to the hw struct
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@ -1158,6 +1270,7 @@ i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
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(struct i40e_aqc_get_link_status *)&desc.params.raw;
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struct i40e_link_status *hw_link_info = &hw->phy.link_info;
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i40e_status status;
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bool tx_pause, rx_pause;
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u16 command_flags;
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i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
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@ -1187,6 +1300,18 @@ i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
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hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
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hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
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/* update fc info */
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tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
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rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
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if (tx_pause & rx_pause)
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hw->fc.current_mode = I40E_FC_FULL;
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else if (tx_pause)
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hw->fc.current_mode = I40E_FC_TX_PAUSE;
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else if (rx_pause)
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hw->fc.current_mode = I40E_FC_RX_PAUSE;
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else
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hw->fc.current_mode = I40E_FC_NONE;
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if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
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hw_link_info->crc_enable = true;
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else
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@ -4326,8 +4326,12 @@ static void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
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static int i40e_up_complete(struct i40e_vsi *vsi)
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{
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struct i40e_pf *pf = vsi->back;
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u8 set_fc_aq_fail = 0;
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int err;
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/* force flow control off */
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i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
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if (pf->flags & I40E_FLAG_MSIX_ENABLED)
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i40e_vsi_configure_msix(vsi);
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else
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@ -8277,7 +8281,6 @@ int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
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**/
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static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
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{
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u32 rxfc = 0, txfc = 0, rxfc_reg;
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int ret;
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/* find out what's out there already */
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@ -8343,62 +8346,7 @@ static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
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/* Initialize user-specific link properties */
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pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
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I40E_AQ_AN_COMPLETED) ? true : false);
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/* requested_mode is set in probe or by ethtool */
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if (!pf->fc_autoneg_status)
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goto no_autoneg;
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if ((pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX) &&
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(pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX))
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pf->hw.fc.current_mode = I40E_FC_FULL;
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else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_TX)
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pf->hw.fc.current_mode = I40E_FC_TX_PAUSE;
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else if (pf->hw.phy.link_info.an_info & I40E_AQ_LINK_PAUSE_RX)
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pf->hw.fc.current_mode = I40E_FC_RX_PAUSE;
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else
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pf->hw.fc.current_mode = I40E_FC_NONE;
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/* sync the flow control settings with the auto-neg values */
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switch (pf->hw.fc.current_mode) {
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case I40E_FC_FULL:
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txfc = 1;
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rxfc = 1;
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break;
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case I40E_FC_TX_PAUSE:
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txfc = 1;
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rxfc = 0;
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break;
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case I40E_FC_RX_PAUSE:
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txfc = 0;
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rxfc = 1;
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break;
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case I40E_FC_NONE:
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case I40E_FC_DEFAULT:
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txfc = 0;
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rxfc = 0;
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break;
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case I40E_FC_PFC:
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/* TBD */
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break;
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/* no default case, we have to handle all possibilities here */
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}
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wr32(&pf->hw, I40E_PRTDCB_FCCFG, txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
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rxfc_reg = rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
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~I40E_PRTDCB_MFLCN_RFCE_MASK;
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rxfc_reg |= (rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT);
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wr32(&pf->hw, I40E_PRTDCB_MFLCN, rxfc_reg);
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goto fc_complete;
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no_autoneg:
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/* disable L2 flow control, user can turn it on if they wish */
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wr32(&pf->hw, I40E_PRTDCB_FCCFG, 0);
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wr32(&pf->hw, I40E_PRTDCB_MFLCN, rd32(&pf->hw, I40E_PRTDCB_MFLCN) &
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~I40E_PRTDCB_MFLCN_RFCE_MASK);
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fc_complete:
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i40e_ptp_init(pf);
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return ret;
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@ -74,6 +74,15 @@ i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
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struct i40e_asq_cmd_details *cmd_details);
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i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw, u16 vsi_id,
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struct i40e_asq_cmd_details *cmd_details);
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enum i40e_status_code i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
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bool qualified_modules, bool report_init,
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struct i40e_aq_get_phy_abilities_resp *abilities,
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struct i40e_asq_cmd_details *cmd_details);
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enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
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struct i40e_aq_set_phy_config *config,
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struct i40e_asq_cmd_details *cmd_details);
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enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
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bool atomic_reset);
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i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
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struct i40e_asq_cmd_details *cmd_details);
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i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
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@ -140,6 +140,14 @@ enum i40e_fc_mode {
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I40E_FC_DEFAULT
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};
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enum i40e_set_fc_aq_failures {
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I40E_SET_FC_AQ_FAIL_NONE = 0,
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I40E_SET_FC_AQ_FAIL_GET = 1,
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I40E_SET_FC_AQ_FAIL_SET = 2,
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I40E_SET_FC_AQ_FAIL_UPDATE = 4,
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I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
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};
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enum i40e_vsi_type {
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I40E_VSI_MAIN = 0,
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I40E_VSI_VMDQ1,
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@ -140,6 +140,14 @@ enum i40e_fc_mode {
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I40E_FC_DEFAULT
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};
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enum i40e_set_fc_aq_failures {
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I40E_SET_FC_AQ_FAIL_NONE = 0,
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I40E_SET_FC_AQ_FAIL_GET = 1,
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I40E_SET_FC_AQ_FAIL_SET = 2,
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I40E_SET_FC_AQ_FAIL_UPDATE = 4,
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I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
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};
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enum i40e_vsi_type {
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I40E_VSI_MAIN = 0,
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I40E_VSI_VMDQ1,
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