MIPS: perf: Change the "mips_perf_event" table unsupported indicator.
Change the indicator from 0xffffffff in the "event_id" member to zero in the "cntr_mask" member. This removes the need to initialize entries that are unsupported. This also solves a problem where the number of entries in the table was increased based on a globel enum used for all platforms, but the new unsupported entries were not added for mips. This was leaving new table entries of all zeros that we not marked UNSUPPORTED. Signed-off-by: Al Cooper <alcooperx@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/4110/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Al Cooper
Ralf Baechle
parent
485172b3df
commit
c5600b2dd9
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@ -78,7 +78,6 @@ struct mips_perf_event {
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static struct mips_perf_event raw_event;
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static DEFINE_MUTEX(raw_event_mutex);
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#define UNSUPPORTED_PERF_EVENT_ID 0xffffffff
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#define C(x) PERF_COUNT_HW_CACHE_##x
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struct mips_pmu {
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@ -664,13 +663,10 @@ static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
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static const struct mips_perf_event *mipspmu_map_general_event(int idx)
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{
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const struct mips_perf_event *pev;
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pev = ((*mipspmu.general_event_map)[idx].event_id ==
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UNSUPPORTED_PERF_EVENT_ID ? ERR_PTR(-EOPNOTSUPP) :
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&(*mipspmu.general_event_map)[idx]);
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return pev;
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if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
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return ERR_PTR(-EOPNOTSUPP);
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return &(*mipspmu.general_event_map)[idx];
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}
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static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
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@ -695,7 +691,7 @@ static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
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[cache_op]
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[cache_result]);
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if (pev->event_id == UNSUPPORTED_PERF_EVENT_ID)
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if (pev->cntr_mask == 0)
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return ERR_PTR(-EOPNOTSUPP);
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return pev;
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@ -800,11 +796,8 @@ static const struct mips_perf_event mipsxxcore_event_map
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[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
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[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
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[PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
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[PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
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[PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
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};
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/* 74K core has different branch event code. */
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@ -812,11 +805,8 @@ static const struct mips_perf_event mipsxx74Kcore_event_map
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[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
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[PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
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[PERF_COUNT_HW_CACHE_REFERENCES] = { UNSUPPORTED_PERF_EVENT_ID },
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[PERF_COUNT_HW_CACHE_MISSES] = { UNSUPPORTED_PERF_EVENT_ID },
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
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[PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
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[PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
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};
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static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
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@ -849,10 +839,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
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[C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
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[C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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@ -869,7 +855,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
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* Note that MIPS has only "hit" events countable for
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* the prefetch operation.
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*/
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(LL)] = {
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@ -881,10 +866,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
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[C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
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[C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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@ -895,10 +876,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
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[C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
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[C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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@ -909,10 +886,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
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[C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
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[C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(BPU)] = {
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/* Using the same code for *HW_BRANCH* */
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@ -924,24 +897,6 @@ static const struct mips_perf_event mipsxxcore_cache_map
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[C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
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[C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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};
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@ -965,10 +920,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
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[C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
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[C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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@ -985,7 +936,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
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* Note that MIPS has only "hit" events countable for
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* the prefetch operation.
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*/
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(LL)] = {
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@ -997,25 +947,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
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[C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
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[C(RESULT_MISS)] = { 0x1d, CNTR_EVEN | CNTR_ODD, P },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(DTLB)] = {
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/* 74K core does not have specific DTLB events. */
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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@ -1026,10 +957,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
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[C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
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[C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(BPU)] = {
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/* Using the same code for *HW_BRANCH* */
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@ -1041,24 +968,6 @@ static const struct mips_perf_event mipsxx74Kcore_cache_map
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[C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
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[C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(NODE)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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};
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@ -1074,39 +983,14 @@ static const struct mips_perf_event octeon_cache_map
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(DTLB)] = {
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@ -1115,46 +999,16 @@ static const struct mips_perf_event octeon_cache_map
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* read and write.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { 0x35, CNTR_ALL },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { 0x35, CNTR_ALL },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { 0x37, CNTR_ALL },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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[C(BPU)] = {
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/* Using the same code for *HW_BRANCH* */
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
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[C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
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},
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},
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};
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