sched, mips, ia64: Remove __ARCH_WANT_UNLOCKED_CTXSW
Kirill found that there's a subtle race in the __ARCH_WANT_UNLOCKED_CTXSW code, and instead of fixing it, remove the entire exception because neither arch that uses it seems to actually still require it. Boot tested on mips64el (qemu) only. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Kirill Tkhai <tkhai@yandex.ru> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Davidlohr Bueso <davidlohr@hp.com> Cc: Fenghua Yu <fenghua.yu@intel.com> Cc: James Hogan <james.hogan@imgtec.com> Cc: Kees Cook <keescook@chromium.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Qais Yousef <qais.yousef@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Tony Luck <tony.luck@intel.com> Cc: oleg@redhat.com Cc: linux@roeck-us.net Cc: linux-ia64@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/20140923150641.GH3312@worktop.programming.kicks-ass.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -19,7 +19,6 @@
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#include <asm/ptrace.h>
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#include <asm/ustack.h>
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#define __ARCH_WANT_UNLOCKED_CTXSW
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#define ARCH_HAS_PREFETCH_SWITCH_STACK
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#define IA64_NUM_PHYS_STACK_REG 96
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@ -397,12 +397,6 @@ unsigned long get_wchan(struct task_struct *p);
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#define ARCH_HAS_PREFETCHW
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#define prefetchw(x) __builtin_prefetch((x), 1, 1)
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/*
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* See Documentation/scheduler/sched-arch.txt; prevents deadlock on SMP
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* systems.
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*/
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#define __ARCH_WANT_UNLOCKED_CTXSW
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#endif
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#endif /* _ASM_PROCESSOR_H */
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@ -2331,10 +2331,6 @@ asmlinkage __visible void schedule_tail(struct task_struct *prev)
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*/
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post_schedule(rq);
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#ifdef __ARCH_WANT_UNLOCKED_CTXSW
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/* In this case, finish_task_switch does not reenable preemption */
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preempt_enable();
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#endif
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if (current->set_child_tid)
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put_user(task_pid_vnr(current), current->set_child_tid);
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}
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@ -2377,9 +2373,7 @@ context_switch(struct rq *rq, struct task_struct *prev,
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* of the scheduler it's an obvious special-case), so we
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* do an early lockdep release here:
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*/
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#ifndef __ARCH_WANT_UNLOCKED_CTXSW
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spin_release(&rq->lock.dep_map, 1, _THIS_IP_);
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#endif
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context_tracking_task_switch(prev, next);
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/* Here we just switch the register state and the stack. */
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@ -975,7 +975,6 @@ static inline int task_on_rq_migrating(struct task_struct *p)
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# define finish_arch_post_lock_switch() do { } while (0)
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#endif
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#ifndef __ARCH_WANT_UNLOCKED_CTXSW
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static inline void prepare_lock_switch(struct rq *rq, struct task_struct *next)
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{
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#ifdef CONFIG_SMP
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@ -1013,35 +1012,6 @@ static inline void finish_lock_switch(struct rq *rq, struct task_struct *prev)
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raw_spin_unlock_irq(&rq->lock);
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}
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#else /* __ARCH_WANT_UNLOCKED_CTXSW */
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static inline void prepare_lock_switch(struct rq *rq, struct task_struct *next)
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{
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#ifdef CONFIG_SMP
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/*
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* We can optimise this out completely for !SMP, because the
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* SMP rebalancing from interrupt is the only thing that cares
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* here.
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*/
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next->on_cpu = 1;
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#endif
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raw_spin_unlock(&rq->lock);
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}
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static inline void finish_lock_switch(struct rq *rq, struct task_struct *prev)
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{
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#ifdef CONFIG_SMP
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/*
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* After ->on_cpu is cleared, the task can be moved to a different CPU.
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* We must ensure this doesn't happen until the switch is completely
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* finished.
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*/
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smp_wmb();
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prev->on_cpu = 0;
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#endif
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local_irq_enable();
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}
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#endif /* __ARCH_WANT_UNLOCKED_CTXSW */
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/*
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* wake flags
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*/
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