ath9k: Simplify node attach/detach routines
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
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b5aa9bf946
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c51701632c
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@ -1366,9 +1366,10 @@ void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta, int if_id)
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an = (struct ath_node *)sta->drv_priv;
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/* set up per-node tx/rx state */
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ath_tx_node_init(sc, an);
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ath_rx_node_init(sc, an);
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if (sc->sc_flags & SC_OP_TXAGGR)
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ath_tx_node_init(sc, an);
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if (sc->sc_flags & SC_OP_RXAGGR)
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ath_rx_node_init(sc, an);
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an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
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sta->ht_cap.ampdu_factor);
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@ -1384,10 +1385,10 @@ void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
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ath_chainmask_sel_timerstop(&an->an_chainmask_sel);
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ath_tx_node_cleanup(sc, an);
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ath_tx_node_free(sc, an);
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ath_rx_node_free(sc, an);
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if (sc->sc_flags & SC_OP_TXAGGR)
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ath_tx_node_cleanup(sc, an);
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if (sc->sc_flags & SC_OP_RXAGGR)
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ath_rx_node_cleanup(sc, an);
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}
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/*
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@ -372,7 +372,7 @@ bool ath_stoprecv(struct ath_softc *sc);
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void ath_flushrecv(struct ath_softc *sc);
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u32 ath_calcrxfilter(struct ath_softc *sc);
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void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an);
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void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an);
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void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an);
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void ath_handle_rx_intr(struct ath_softc *sc);
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int ath_rx_init(struct ath_softc *sc, int nbufs);
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void ath_rx_cleanup(struct ath_softc *sc);
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@ -1200,61 +1200,56 @@ void ath_rx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid)
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void ath_rx_node_init(struct ath_softc *sc, struct ath_node *an)
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{
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if (sc->sc_flags & SC_OP_RXAGGR) {
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struct ath_arx_tid *rxtid;
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int tidno;
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struct ath_arx_tid *rxtid;
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int tidno;
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/* Init per tid rx state */
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for (tidno = 0, rxtid = &an->an_aggr.rx.tid[tidno];
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tidno < WME_NUM_TID;
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tidno++, rxtid++) {
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rxtid->an = an;
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rxtid->seq_reset = 1;
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rxtid->seq_next = 0;
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rxtid->baw_size = WME_MAX_BA;
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rxtid->baw_head = rxtid->baw_tail = 0;
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/* Init per tid rx state */
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for (tidno = 0, rxtid = &an->an_aggr.rx.tid[tidno];
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tidno < WME_NUM_TID;
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tidno++, rxtid++) {
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rxtid->an = an;
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rxtid->seq_reset = 1;
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rxtid->seq_next = 0;
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rxtid->baw_size = WME_MAX_BA;
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rxtid->baw_head = rxtid->baw_tail = 0;
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/*
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* Ensure the buffer pointer is null at this point
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* (needs to be allocated when addba is received)
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*/
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/*
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* Ensure the buffer pointer is null at this point
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* (needs to be allocated when addba is received)
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*/
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rxtid->rxbuf = NULL;
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setup_timer(&rxtid->timer, ath_rx_timer,
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(unsigned long)rxtid);
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spin_lock_init(&rxtid->tidlock);
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rxtid->rxbuf = NULL;
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setup_timer(&rxtid->timer, ath_rx_timer,
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(unsigned long)rxtid);
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spin_lock_init(&rxtid->tidlock);
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/* ADDBA state */
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rxtid->addba_exchangecomplete = 0;
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}
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/* ADDBA state */
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rxtid->addba_exchangecomplete = 0;
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}
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}
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void ath_rx_node_free(struct ath_softc *sc, struct ath_node *an)
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void ath_rx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
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{
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if (sc->sc_flags & SC_OP_RXAGGR) {
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struct ath_arx_tid *rxtid;
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int tidno, i;
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struct ath_arx_tid *rxtid;
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int tidno, i;
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/* Init per tid rx state */
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for (tidno = 0, rxtid = &an->an_aggr.rx.tid[tidno];
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tidno < WME_NUM_TID;
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tidno++, rxtid++) {
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/* Init per tid rx state */
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for (tidno = 0, rxtid = &an->an_aggr.rx.tid[tidno];
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tidno < WME_NUM_TID;
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tidno++, rxtid++) {
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if (!rxtid->addba_exchangecomplete)
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continue;
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if (!rxtid->addba_exchangecomplete)
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continue;
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/* must cancel timer first */
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del_timer_sync(&rxtid->timer);
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/* must cancel timer first */
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del_timer_sync(&rxtid->timer);
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/* drop any pending sub-frames */
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ath_rx_flush_tid(sc, rxtid, 1);
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/* drop any pending sub-frames */
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ath_rx_flush_tid(sc, rxtid, 1);
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for (i = 0; i < ATH_TID_MAX_BUFS; i++)
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ASSERT(rxtid->rxbuf[i].rx_wbuf == NULL);
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for (i = 0; i < ATH_TID_MAX_BUFS; i++)
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ASSERT(rxtid->rxbuf[i].rx_wbuf == NULL);
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rxtid->addba_exchangecomplete = 0;
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}
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rxtid->addba_exchangecomplete = 0;
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}
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}
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@ -2565,62 +2565,60 @@ void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
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void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
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{
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if (sc->sc_flags & SC_OP_TXAGGR) {
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struct ath_atx_tid *tid;
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struct ath_atx_ac *ac;
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int tidno, acno;
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struct ath_atx_tid *tid;
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struct ath_atx_ac *ac;
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int tidno, acno;
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/*
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* Init per tid tx state
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*/
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for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
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tidno < WME_NUM_TID;
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tidno++, tid++) {
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tid->an = an;
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tid->tidno = tidno;
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tid->seq_start = tid->seq_next = 0;
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tid->baw_size = WME_MAX_BA;
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tid->baw_head = tid->baw_tail = 0;
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tid->sched = false;
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tid->paused = false;
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tid->cleanup_inprogress = false;
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INIT_LIST_HEAD(&tid->buf_q);
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/*
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* Init per tid tx state
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*/
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for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
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tidno < WME_NUM_TID;
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tidno++, tid++) {
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tid->an = an;
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tid->tidno = tidno;
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tid->seq_start = tid->seq_next = 0;
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tid->baw_size = WME_MAX_BA;
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tid->baw_head = tid->baw_tail = 0;
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tid->sched = false;
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tid->paused = false;
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tid->cleanup_inprogress = false;
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INIT_LIST_HEAD(&tid->buf_q);
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acno = TID_TO_WME_AC(tidno);
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tid->ac = &an->an_aggr.tx.ac[acno];
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acno = TID_TO_WME_AC(tidno);
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tid->ac = &an->an_aggr.tx.ac[acno];
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/* ADDBA state */
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tid->addba_exchangecomplete = 0;
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tid->addba_exchangeinprogress = 0;
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tid->addba_exchangeattempts = 0;
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}
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/* ADDBA state */
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tid->addba_exchangecomplete = 0;
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tid->addba_exchangeinprogress = 0;
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tid->addba_exchangeattempts = 0;
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}
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/*
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* Init per ac tx state
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*/
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for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
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acno < WME_NUM_AC; acno++, ac++) {
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ac->sched = false;
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INIT_LIST_HEAD(&ac->tid_q);
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/*
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* Init per ac tx state
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*/
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for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
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acno < WME_NUM_AC; acno++, ac++) {
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ac->sched = false;
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INIT_LIST_HEAD(&ac->tid_q);
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switch (acno) {
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case WME_AC_BE:
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ac->qnum = ath_tx_get_qnum(sc,
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ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
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break;
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case WME_AC_BK:
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ac->qnum = ath_tx_get_qnum(sc,
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ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
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break;
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case WME_AC_VI:
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ac->qnum = ath_tx_get_qnum(sc,
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ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
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break;
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case WME_AC_VO:
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ac->qnum = ath_tx_get_qnum(sc,
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ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
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break;
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}
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switch (acno) {
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case WME_AC_BE:
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ac->qnum = ath_tx_get_qnum(sc,
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ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
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break;
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case WME_AC_BK:
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ac->qnum = ath_tx_get_qnum(sc,
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ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
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break;
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case WME_AC_VI:
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ac->qnum = ath_tx_get_qnum(sc,
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ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
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break;
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case WME_AC_VO:
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ac->qnum = ath_tx_get_qnum(sc,
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ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
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break;
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}
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}
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}
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@ -2664,25 +2662,6 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
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}
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}
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/* Cleanup per node transmit state */
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void ath_tx_node_free(struct ath_softc *sc, struct ath_node *an)
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{
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if (sc->sc_flags & SC_OP_TXAGGR) {
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struct ath_atx_tid *tid;
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int tidno, i;
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/* Init per tid rx state */
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for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
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tidno < WME_NUM_TID;
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tidno++, tid++) {
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for (i = 0; i < ATH_TID_MAX_BUFS; i++)
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ASSERT(tid->tx_buf[i] == NULL);
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}
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}
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}
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void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
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{
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int hdrlen, padsize;
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