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drm/gk20a/clk: fix max VCO value 

For some reason max_vco was set to a lower value that it can support,
which prevented some clock states to be applied. Fix this by setting it
to the same value as downstream.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot 2014-11-13 18:07:27 +09:00 committed by Ben Skeggs
parent 50ab2e5206
commit c50d3b2b4a
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/nouveau/core/subdev/clock/gk20a.c
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@ -109,7 +109,7 @@ struct gk20a_clk_pllg_params {
};
static const struct gk20a_clk_pllg_params gk20a_pllg_params = {
.min_vco = 1000, .max_vco = 1700,
.min_vco = 1000, .max_vco = 2064,
.min_u = 12, .max_u = 38,
.min_m = 1, .max_m = 255,
.min_n = 8, .max_n = 255,