riscv: dts: microchip: refactor icicle kit device tree
Assorted minor changes to the MPFS/Icicle kit device tree: - rename serial to mmuart to match microchip documentation - move phy0 inside mac1 node to match phy configuration - add labels where missing (cpus, cache controller) - add missing address cells & interrupts to MACs Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
Conor Dooley
Palmer Dabbelt
parent
72560c6559
commit
c5094f3710
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@ -1,5 +1,5 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020 Microchip Technology Inc */
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/dts-v1/;
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@ -13,11 +13,11 @@
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compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
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aliases {
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ethernet0 = &emac1;
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serial0 = &serial0;
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serial1 = &serial1;
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serial2 = &serial2;
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serial3 = &serial3;
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ethernet0 = &mac1;
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serial0 = &mmuart0;
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serial1 = &mmuart1;
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serial2 = &mmuart2;
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serial3 = &mmuart3;
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};
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chosen {
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@ -39,19 +39,19 @@
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clock-frequency = <600000000>;
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};
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&serial0 {
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&mmuart0 {
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status = "okay";
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};
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&serial1 {
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&mmuart1 {
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status = "okay";
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};
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&serial2 {
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&mmuart2 {
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status = "okay";
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};
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&serial3 {
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&mmuart3 {
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status = "okay";
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};
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@ -61,7 +61,10 @@
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bus-width = <4>;
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disable-wp;
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cap-sd-highspeed;
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cap-mmc-highspeed;
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card-detect-delay = <200>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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@ -72,22 +75,22 @@
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status = "okay";
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};
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&emac0 {
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&mac0 {
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phy-mode = "sgmii";
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phy-handle = <&phy0>;
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phy0: ethernet-phy@8 {
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reg = <8>;
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ti,fifo-depth = <0x01>;
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};
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};
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&emac1 {
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&mac1 {
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status = "okay";
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phy-mode = "sgmii";
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phy-handle = <&phy1>;
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phy1: ethernet-phy@9 {
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reg = <9>;
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ti,fifo-depth = <0x01>;
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ti,fifo-depth = <0x1>;
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};
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phy0: ethernet-phy@8 {
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reg = <8>;
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ti,fifo-depth = <0x1>;
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};
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};
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@ -1,5 +1,5 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2020 Microchip Technology Inc */
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/* Copyright (c) 2020-2021 Microchip Technology Inc */
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/dts-v1/;
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#include "dt-bindings/clock/microchip,mpfs-clock.h"
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@ -15,7 +15,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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cpu0: cpu@0 {
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compatible = "sifive,e51", "sifive,rocket0", "riscv";
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device_type = "cpu";
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i-cache-block-size = <64>;
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@ -33,7 +33,7 @@
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};
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};
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cpu@1 {
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cpu1: cpu@1 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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@ -60,7 +60,7 @@
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};
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};
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cpu@2 {
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cpu2: cpu@2 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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@ -87,7 +87,7 @@
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};
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};
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cpu@3 {
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cpu3: cpu@3 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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@ -114,7 +114,7 @@
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};
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};
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cpu@4 {
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cpu4: cpu@4 {
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compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
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d-cache-block-size = <64>;
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d-cache-sets = <64>;
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@ -152,8 +152,9 @@
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compatible = "simple-bus";
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ranges;
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cache-controller@2010000 {
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cctrllr: cache-controller@2010000 {
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compatible = "sifive,fu540-c000-ccache", "cache";
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reg = <0x0 0x2010000 0x0 0x1000>;
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cache-block-size = <64>;
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cache-level = <2>;
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cache-sets = <1024>;
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@ -161,10 +162,9 @@
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cache-unified;
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interrupt-parent = <&plic>;
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interrupts = <1>, <2>, <3>;
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reg = <0x0 0x2010000 0x0 0x1000>;
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};
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clint@2000000 {
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clint: clint@2000000 {
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compatible = "sifive,fu540-c000-clint", "sifive,clint0";
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reg = <0x0 0x2000000 0x0 0xC000>;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
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@ -174,6 +174,15 @@
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<&cpu4_intc 3>, <&cpu4_intc 7>;
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};
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dma@3000000 {
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compatible = "sifive,fu540-c000-pdma";
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reg = <0x0 0x3000000 0x0 0x8000>;
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interrupt-parent = <&plic>;
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interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
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<30>;
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#dma-cells = <1>;
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};
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plic: interrupt-controller@c000000 {
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compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
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reg = <0x0 0xc000000 0x0 0x4000000>;
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@ -188,15 +197,6 @@
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riscv,ndev = <186>;
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};
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dma@3000000 {
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compatible = "sifive,fu540-c000-pdma";
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reg = <0x0 0x3000000 0x0 0x8000>;
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interrupt-parent = <&plic>;
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interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
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<30>;
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#dma-cells = <1>;
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};
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clkcfg: clkcfg@20002000 {
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compatible = "microchip,mpfs-clkcfg";
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reg = <0x0 0x20002000 0x0 0x1000>;
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@ -204,7 +204,7 @@
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#clock-cells = <1>;
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};
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serial0: serial@20000000 {
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mmuart0: serial@20000000 {
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compatible = "ns16550a";
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reg = <0x0 0x20000000 0x0 0x400>;
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reg-io-width = <4>;
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@ -216,7 +216,7 @@
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status = "disabled";
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};
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serial1: serial@20100000 {
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mmuart1: serial@20100000 {
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compatible = "ns16550a";
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reg = <0x0 0x20100000 0x0 0x400>;
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reg-io-width = <4>;
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@ -228,7 +228,7 @@
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status = "disabled";
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};
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serial2: serial@20102000 {
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mmuart2: serial@20102000 {
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compatible = "ns16550a";
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reg = <0x0 0x20102000 0x0 0x400>;
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reg-io-width = <4>;
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@ -240,7 +240,7 @@
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status = "disabled";
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};
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serial3: serial@20104000 {
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mmuart3: serial@20104000 {
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compatible = "ns16550a";
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reg = <0x0 0x20104000 0x0 0x400>;
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reg-io-width = <4>;
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@ -257,37 +257,36 @@
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compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
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reg = <0x0 0x20008000 0x0 0x1000>;
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interrupt-parent = <&plic>;
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interrupts = <88>, <89>;
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interrupts = <88>;
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clocks = <&clkcfg CLK_MMC>;
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max-frequency = <200000000>;
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status = "disabled";
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};
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emac0: ethernet@20110000 {
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mac0: ethernet@20110000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20110000 0x0 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <64>, <65>, <66>, <67>;
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interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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emac1: ethernet@20112000 {
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mac1: ethernet@20112000 {
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compatible = "cdns,macb";
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reg = <0x0 0x20112000 0x0 0x2000>;
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interrupt-parent = <&plic>;
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interrupts = <70>, <71>, <72>, <73>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
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status = "disabled";
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clock-names = "pclk", "hclk";
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#address-cells = <1>;
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#size-cells = <0>;
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interrupt-parent = <&plic>;
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interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
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clock-names = "pclk", "hclk";
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status = "disabled";
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};
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};
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};
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