[AGPGART] intel_agp: cleanup intel private data
Remove volatile type declare for IO mem variables. A single private gart data is used by all drivers, this makes it clean. Eric Anholt wrote the original patch. Signed-off-by: Wang Zhenyu <zhenyu.z.wang@intel.com> Signed-off-by: Dave Jones <davej@redhat.com>
This commit is contained in:
Wang Zhenyu
Dave Jones
parent
bbdfff86a8
commit
c4ca881796
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@ -86,11 +86,18 @@ static struct gatt_mask intel_i810_masks[] =
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.type = INTEL_AGP_CACHED_MEMORY}
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};
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static struct _intel_i810_private {
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struct pci_dev *i810_dev; /* device one */
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volatile u8 __iomem *registers;
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static struct _intel_private {
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struct pci_dev *pcidev; /* device one */
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u8 __iomem *registers;
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u32 __iomem *gtt; /* I915G */
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int num_dcache_entries;
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} intel_i810_private;
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/* gtt_entries is the number of gtt entries that are already mapped
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* to stolen memory. Stolen memory is larger than the memory mapped
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* through gtt_entries, as it includes some reserved space for the BIOS
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* popup and for the GTT.
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*/
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int gtt_entries; /* i830+ */
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} intel_private;
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static int intel_i810_fetch_size(void)
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{
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@ -127,32 +134,32 @@ static int intel_i810_configure(void)
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current_size = A_SIZE_FIX(agp_bridge->current_size);
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if (!intel_i810_private.registers) {
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pci_read_config_dword(intel_i810_private.i810_dev, I810_MMADDR, &temp);
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if (!intel_private.registers) {
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pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
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temp &= 0xfff80000;
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intel_i810_private.registers = ioremap(temp, 128 * 4096);
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if (!intel_i810_private.registers) {
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intel_private.registers = ioremap(temp, 128 * 4096);
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if (!intel_private.registers) {
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printk(KERN_ERR PFX "Unable to remap memory.\n");
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return -ENOMEM;
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}
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}
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if ((readl(intel_i810_private.registers+I810_DRAM_CTL)
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if ((readl(intel_private.registers+I810_DRAM_CTL)
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& I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
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/* This will need to be dynamically assigned */
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printk(KERN_INFO PFX "detected 4MB dedicated video ram.\n");
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intel_i810_private.num_dcache_entries = 1024;
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intel_private.num_dcache_entries = 1024;
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}
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pci_read_config_dword(intel_i810_private.i810_dev, I810_GMADDR, &temp);
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pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_i810_private.registers+I810_PGETBL_CTL);
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readl(intel_i810_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
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writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
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readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
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if (agp_bridge->driver->needs_scratch_page) {
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for (i = 0; i < current_size->num_entries; i++) {
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writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
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readl(intel_i810_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
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writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
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readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI posting. */
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}
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}
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global_cache_flush();
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@ -161,9 +168,9 @@ static int intel_i810_configure(void)
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static void intel_i810_cleanup(void)
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{
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writel(0, intel_i810_private.registers+I810_PGETBL_CTL);
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readl(intel_i810_private.registers); /* PCI Posting. */
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iounmap(intel_i810_private.registers);
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writel(0, intel_private.registers+I810_PGETBL_CTL);
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readl(intel_private.registers); /* PCI Posting. */
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iounmap(intel_private.registers);
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}
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static void intel_i810_tlbflush(struct agp_memory *mem)
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@ -261,9 +268,9 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
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global_cache_flush();
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for (i = pg_start; i < (pg_start + mem->page_count); i++) {
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writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
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intel_i810_private.registers+I810_PTE_BASE+(i*4));
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intel_private.registers+I810_PTE_BASE+(i*4));
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}
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readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4));
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readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
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break;
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case AGP_PHYS_MEMORY:
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case AGP_NORMAL_MEMORY:
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@ -273,9 +280,9 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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mem->memory[i],
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mask_type),
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intel_i810_private.registers+I810_PTE_BASE+(j*4));
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intel_private.registers+I810_PTE_BASE+(j*4));
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}
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readl(intel_i810_private.registers+I810_PTE_BASE+((j-1)*4));
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readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
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break;
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default:
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goto out_err;
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@ -298,9 +305,9 @@ static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
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return 0;
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for (i = pg_start; i < (mem->page_count + pg_start); i++) {
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writel(agp_bridge->scratch_page, intel_i810_private.registers+I810_PTE_BASE+(i*4));
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writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
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}
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readl(intel_i810_private.registers+I810_PTE_BASE+((i-1)*4));
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readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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@ -354,7 +361,7 @@ static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
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struct agp_memory *new;
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if (type == AGP_DCACHE_MEMORY) {
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if (pg_count != intel_i810_private.num_dcache_entries)
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if (pg_count != intel_private.num_dcache_entries)
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return NULL;
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new = agp_create_memory(1);
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@ -404,18 +411,6 @@ static struct aper_size_info_fixed intel_i830_sizes[] =
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{512, 131072, 7},
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};
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static struct _intel_i830_private {
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struct pci_dev *i830_dev; /* device one */
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volatile u8 __iomem *registers;
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volatile u32 __iomem *gtt; /* I915G */
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/* gtt_entries is the number of gtt entries that are already mapped
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* to stolen memory. Stolen memory is larger than the memory mapped
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* through gtt_entries, as it includes some reserved space for the BIOS
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* popup and for the GTT.
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*/
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int gtt_entries;
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} intel_i830_private;
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static void intel_i830_init_gtt_entries(void)
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{
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u16 gmch_ctrl;
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@ -429,7 +424,7 @@ static void intel_i830_init_gtt_entries(void)
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if (IS_I965) {
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u32 pgetbl_ctl;
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pgetbl_ctl = readl(intel_i830_private.registers+I810_PGETBL_CTL);
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pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
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/* The 965 has a field telling us the size of the GTT,
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* which may be larger than what is necessary to map the
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@ -471,7 +466,7 @@ static void intel_i830_init_gtt_entries(void)
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gtt_entries = MB(8) - KB(size);
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break;
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case I830_GMCH_GMS_LOCAL:
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rdct = readb(intel_i830_private.registers+I830_RDRAM_CHANNEL_TYPE);
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rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
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gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
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MB(ddt[I830_RDRAM_DDT(rdct)]);
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local = 1;
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@ -529,7 +524,7 @@ static void intel_i830_init_gtt_entries(void)
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"No pre-allocated video memory detected.\n");
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gtt_entries /= KB(4);
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intel_i830_private.gtt_entries = gtt_entries;
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intel_private.gtt_entries = gtt_entries;
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}
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/* The intel i830 automatically initializes the agp aperture during POST.
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@ -547,14 +542,14 @@ static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
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num_entries = size->num_entries;
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agp_bridge->gatt_table_real = NULL;
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pci_read_config_dword(intel_i830_private.i830_dev,I810_MMADDR,&temp);
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pci_read_config_dword(intel_private.pcidev,I810_MMADDR,&temp);
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temp &= 0xfff80000;
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intel_i830_private.registers = ioremap(temp,128 * 4096);
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if (!intel_i830_private.registers)
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intel_private.registers = ioremap(temp,128 * 4096);
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if (!intel_private.registers)
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return -ENOMEM;
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temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
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temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
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global_cache_flush(); /* FIXME: ?? */
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/* we have to call this as early as possible after the MMIO base address is known */
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@ -614,20 +609,20 @@ static int intel_i830_configure(void)
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current_size = A_SIZE_FIX(agp_bridge->current_size);
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pci_read_config_dword(intel_i830_private.i830_dev,I810_GMADDR,&temp);
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pci_read_config_dword(intel_private.pcidev,I810_GMADDR,&temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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pci_read_config_word(agp_bridge->dev,I830_GMCH_CTRL,&gmch_ctrl);
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gmch_ctrl |= I830_GMCH_ENABLED;
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pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
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writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
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readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
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writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
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readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
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if (agp_bridge->driver->needs_scratch_page) {
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for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
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writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
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readl(intel_i830_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
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for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
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writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
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readl(intel_private.registers+I810_PTE_BASE+(i*4)); /* PCI Posting. */
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}
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}
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@ -637,7 +632,7 @@ static int intel_i830_configure(void)
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static void intel_i830_cleanup(void)
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{
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iounmap(intel_i830_private.registers);
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iounmap(intel_private.registers);
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}
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static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int type)
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@ -653,9 +648,9 @@ static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int
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temp = agp_bridge->current_size;
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num_entries = A_SIZE_FIX(temp)->num_entries;
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if (pg_start < intel_i830_private.gtt_entries) {
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printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
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pg_start,intel_i830_private.gtt_entries);
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if (pg_start < intel_private.gtt_entries) {
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printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
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pg_start,intel_private.gtt_entries);
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printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
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goto out_err;
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@ -683,9 +678,9 @@ static int intel_i830_insert_entries(struct agp_memory *mem,off_t pg_start, int
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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mem->memory[i], mask_type),
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intel_i830_private.registers+I810_PTE_BASE+(j*4));
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intel_private.registers+I810_PTE_BASE+(j*4));
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}
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readl(intel_i830_private.registers+I810_PTE_BASE+((j-1)*4));
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readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
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agp_bridge->driver->tlb_flush(mem);
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out:
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@ -703,15 +698,15 @@ static int intel_i830_remove_entries(struct agp_memory *mem,off_t pg_start,
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if (mem->page_count == 0)
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return 0;
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if (pg_start < intel_i830_private.gtt_entries) {
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if (pg_start < intel_private.gtt_entries) {
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printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
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return -EINVAL;
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}
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for (i = pg_start; i < (mem->page_count + pg_start); i++) {
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writel(agp_bridge->scratch_page, intel_i830_private.registers+I810_PTE_BASE+(i*4));
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writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
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}
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readl(intel_i830_private.registers+I810_PTE_BASE+((i-1)*4));
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readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
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agp_bridge->driver->tlb_flush(mem);
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return 0;
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@ -734,7 +729,7 @@ static int intel_i915_configure(void)
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current_size = A_SIZE_FIX(agp_bridge->current_size);
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pci_read_config_dword(intel_i830_private.i830_dev, I915_GMADDR, &temp);
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pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
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agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
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@ -742,13 +737,13 @@ static int intel_i915_configure(void)
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gmch_ctrl |= I830_GMCH_ENABLED;
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pci_write_config_word(agp_bridge->dev,I830_GMCH_CTRL,gmch_ctrl);
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writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_i830_private.registers+I810_PGETBL_CTL);
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readl(intel_i830_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
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writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
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readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
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if (agp_bridge->driver->needs_scratch_page) {
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for (i = intel_i830_private.gtt_entries; i < current_size->num_entries; i++) {
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writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
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readl(intel_i830_private.gtt+i); /* PCI Posting. */
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for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
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writel(agp_bridge->scratch_page, intel_private.gtt+i);
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readl(intel_private.gtt+i); /* PCI Posting. */
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}
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}
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@ -758,8 +753,8 @@ static int intel_i915_configure(void)
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static void intel_i915_cleanup(void)
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{
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iounmap(intel_i830_private.gtt);
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iounmap(intel_i830_private.registers);
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iounmap(intel_private.gtt);
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iounmap(intel_private.registers);
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}
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static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
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@ -776,9 +771,9 @@ static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
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temp = agp_bridge->current_size;
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num_entries = A_SIZE_FIX(temp)->num_entries;
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if (pg_start < intel_i830_private.gtt_entries) {
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printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_i830_private.gtt_entries == 0x%.8x\n",
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pg_start,intel_i830_private.gtt_entries);
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if (pg_start < intel_private.gtt_entries) {
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printk (KERN_DEBUG PFX "pg_start == 0x%.8lx,intel_private.gtt_entries == 0x%.8x\n",
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pg_start,intel_private.gtt_entries);
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printk (KERN_INFO PFX "Trying to insert into local/stolen memory\n");
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goto out_err;
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@ -805,10 +800,10 @@ static int intel_i915_insert_entries(struct agp_memory *mem,off_t pg_start,
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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mem->memory[i], mask_type), intel_i830_private.gtt+j);
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mem->memory[i], mask_type), intel_private.gtt+j);
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}
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readl(intel_i830_private.gtt+j-1);
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readl(intel_private.gtt+j-1);
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agp_bridge->driver->tlb_flush(mem);
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out:
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@ -826,15 +821,15 @@ static int intel_i915_remove_entries(struct agp_memory *mem,off_t pg_start,
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if (mem->page_count == 0)
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||||
return 0;
|
||||
|
||||
if (pg_start < intel_i830_private.gtt_entries) {
|
||||
if (pg_start < intel_private.gtt_entries) {
|
||||
printk (KERN_INFO PFX "Trying to disable local/stolen memory\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = pg_start; i < (mem->page_count + pg_start); i++) {
|
||||
writel(agp_bridge->scratch_page, intel_i830_private.gtt+i);
|
||||
writel(agp_bridge->scratch_page, intel_private.gtt+i);
|
||||
}
|
||||
readl(intel_i830_private.gtt+i-1);
|
||||
readl(intel_private.gtt+i-1);
|
||||
|
||||
agp_bridge->driver->tlb_flush(mem);
|
||||
return 0;
|
||||
|
|
@ -850,7 +845,7 @@ static int intel_i9xx_fetch_size(void)
|
|||
int aper_size; /* size in megabytes */
|
||||
int i;
|
||||
|
||||
aper_size = pci_resource_len(intel_i830_private.i830_dev, 2) / MB(1);
|
||||
aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
|
||||
|
||||
for (i = 0; i < num_sizes; i++) {
|
||||
if (aper_size == intel_i830_sizes[i].size) {
|
||||
|
|
@ -878,20 +873,20 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
|
|||
num_entries = size->num_entries;
|
||||
agp_bridge->gatt_table_real = NULL;
|
||||
|
||||
pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
|
||||
pci_read_config_dword(intel_i830_private.i830_dev, I915_PTEADDR,&temp2);
|
||||
pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
|
||||
pci_read_config_dword(intel_private.pcidev, I915_PTEADDR,&temp2);
|
||||
|
||||
intel_i830_private.gtt = ioremap(temp2, 256 * 1024);
|
||||
if (!intel_i830_private.gtt)
|
||||
intel_private.gtt = ioremap(temp2, 256 * 1024);
|
||||
if (!intel_private.gtt)
|
||||
return -ENOMEM;
|
||||
|
||||
temp &= 0xfff80000;
|
||||
|
||||
intel_i830_private.registers = ioremap(temp,128 * 4096);
|
||||
if (!intel_i830_private.registers)
|
||||
intel_private.registers = ioremap(temp,128 * 4096);
|
||||
if (!intel_private.registers)
|
||||
return -ENOMEM;
|
||||
|
||||
temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
|
||||
temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
|
||||
global_cache_flush(); /* FIXME: ? */
|
||||
|
||||
/* we have to call this as early as possible after the MMIO base address is known */
|
||||
|
|
@ -938,20 +933,20 @@ static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
|
|||
num_entries = size->num_entries;
|
||||
agp_bridge->gatt_table_real = NULL;
|
||||
|
||||
pci_read_config_dword(intel_i830_private.i830_dev, I915_MMADDR, &temp);
|
||||
pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
|
||||
|
||||
temp &= 0xfff00000;
|
||||
intel_i830_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
|
||||
intel_private.gtt = ioremap((temp + (512 * 1024)) , 512 * 1024);
|
||||
|
||||
if (!intel_i830_private.gtt)
|
||||
if (!intel_private.gtt)
|
||||
return -ENOMEM;
|
||||
|
||||
|
||||
intel_i830_private.registers = ioremap(temp,128 * 4096);
|
||||
if (!intel_i830_private.registers)
|
||||
intel_private.registers = ioremap(temp,128 * 4096);
|
||||
if (!intel_private.registers)
|
||||
return -ENOMEM;
|
||||
|
||||
temp = readl(intel_i830_private.registers+I810_PGETBL_CTL) & 0xfffff000;
|
||||
temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
|
||||
global_cache_flush(); /* FIXME: ? */
|
||||
|
||||
/* we have to call this as early as possible after the MMIO base address is known */
|
||||
|
|
@ -1729,7 +1724,7 @@ static int find_i810(u16 device)
|
|||
i810_dev = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
|
||||
if (!i810_dev)
|
||||
return 0;
|
||||
intel_i810_private.i810_dev = i810_dev;
|
||||
intel_private.pcidev = i810_dev;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -1746,7 +1741,7 @@ static int find_i830(u16 device)
|
|||
if (!i830_dev)
|
||||
return 0;
|
||||
|
||||
intel_i830_private.i830_dev = i830_dev;
|
||||
intel_private.pcidev = i830_dev;
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
|
@ -1946,11 +1941,7 @@ static int __devinit agp_intel_probe(struct pci_dev *pdev,
|
|||
|
||||
bridge->dev = pdev;
|
||||
bridge->capndx = cap_ptr;
|
||||
|
||||
if (bridge->driver == &intel_810_driver)
|
||||
bridge->dev_private_data = &intel_i810_private;
|
||||
else if (bridge->driver == &intel_830_driver)
|
||||
bridge->dev_private_data = &intel_i830_private;
|
||||
bridge->dev_private_data = &intel_private;
|
||||
|
||||
printk(KERN_INFO PFX "Detected an Intel %s Chipset.\n", name);
|
||||
|
||||
|
|
@ -2002,10 +1993,8 @@ static void __devexit agp_intel_remove(struct pci_dev *pdev)
|
|||
|
||||
agp_remove_bridge(bridge);
|
||||
|
||||
if (intel_i810_private.i810_dev)
|
||||
pci_dev_put(intel_i810_private.i810_dev);
|
||||
if (intel_i830_private.i830_dev)
|
||||
pci_dev_put(intel_i830_private.i830_dev);
|
||||
if (intel_private.pcidev)
|
||||
pci_dev_put(intel_private.pcidev);
|
||||
|
||||
agp_put_bridge(bridge);
|
||||
}
|
||||
|
|
@ -2021,10 +2010,8 @@ static int agp_intel_resume(struct pci_dev *pdev)
|
|||
* as host bridge (00:00) resumes before graphics device (02:00),
|
||||
* then our access to its pci space can work right.
|
||||
*/
|
||||
if (intel_i810_private.i810_dev)
|
||||
pci_restore_state(intel_i810_private.i810_dev);
|
||||
if (intel_i830_private.i830_dev)
|
||||
pci_restore_state(intel_i830_private.i830_dev);
|
||||
if (intel_private.pcidev)
|
||||
pci_restore_state(intel_private.pcidev);
|
||||
|
||||
if (bridge->driver == &intel_generic_driver)
|
||||
intel_configure();
|
||||
|
|
|
|||
Loading…
Reference in New Issue