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drm/nouveau/svm: use NVIDIA's headers for migrate_clear() 

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs 2020-06-22 19:27:00 +10:00
parent 66c3bdd4e7
commit c47fceca2e
1 changed files with 33 additions and 19 deletions
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52
drivers/gpu/drm/nouveau/nouveau_dmem.c
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@ -462,15 +462,7 @@ nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length,
enum nouveau_aper dst_aper, u64 dst_addr)
{
struct nvif_push *push = drm->dmem->migrate.chan->chan.push;
u32 launch_dma = (1 << 10) /* REMAP_ENABLE_TRUE */ |
(1 << 8) /* DST_MEMORY_LAYOUT_PITCH. */ |
(1 << 7) /* SRC_MEMORY_LAYOUT_PITCH. */ |
(1 << 2) /* FLUSH_ENABLE_TRUE. */ |
(2 << 0) /* DATA_TRANSFER_TYPE_NON_PIPELINED. */;
u32 remap = (4 << 0) /* DST_X_CONST_A */ |
(5 << 4) /* DST_Y_CONST_B */ |
(3 << 16) /* COMPONENT_SIZE_FOUR */ |
(1 << 24) /* NUM_DST_COMPONENTS_TWO */;
u32 launch_dma = 0;
int ret;
ret = PUSH_WAIT(push, 12);
@ -479,23 +471,45 @@ nvc0b5_migrate_clear(struct nouveau_drm *drm, u32 length,
switch (dst_aper) {
case NOUVEAU_APER_VRAM:
PUSH_NVIM(push, NVA0B5, 0x0264, 0);
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, LOCAL_FB));
break;
case NOUVEAU_APER_HOST:
PUSH_NVIM(push, NVA0B5, 0x0264, 1);
PUSH_IMMD(push, NVA0B5, SET_DST_PHYS_MODE,
NVDEF(NVA0B5, SET_DST_PHYS_MODE, TARGET, COHERENT_SYSMEM));
break;
default:
return -EINVAL;
}
launch_dma |= 0x00002000; /* DST_TYPE_PHYSICAL. */
PUSH_NVSQ(push, NVA0B5, 0x0700, 0,
0x0704, 0,
0x0708, remap);
PUSH_NVSQ(push, NVA0B5, 0x0408, upper_32_bits(dst_addr),
0x040c, lower_32_bits(dst_addr));
PUSH_NVSQ(push, NVA0B5, 0x0418, length >> 3);
PUSH_NVSQ(push, NVA0B5, 0x0300, launch_dma);
launch_dma |= NVDEF(NVA0B5, LAUNCH_DMA, DST_TYPE, PHYSICAL);
PUSH_MTHD(push, NVA0B5, SET_REMAP_CONST_A, 0,
SET_REMAP_CONST_B, 0,
SET_REMAP_COMPONENTS,
NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_X, CONST_A) |
NVDEF(NVA0B5, SET_REMAP_COMPONENTS, DST_Y, CONST_B) |
NVDEF(NVA0B5, SET_REMAP_COMPONENTS, COMPONENT_SIZE, FOUR) |
NVDEF(NVA0B5, SET_REMAP_COMPONENTS, NUM_DST_COMPONENTS, TWO));
PUSH_MTHD(push, NVA0B5, OFFSET_OUT_UPPER,
NVVAL(NVA0B5, OFFSET_OUT_UPPER, UPPER, upper_32_bits(dst_addr)),
OFFSET_OUT_LOWER, lower_32_bits(dst_addr));
PUSH_MTHD(push, NVA0B5, LINE_LENGTH_IN, length >> 3);
PUSH_MTHD(push, NVA0B5, LAUNCH_DMA, launch_dma |
NVDEF(NVA0B5, LAUNCH_DMA, DATA_TRANSFER_TYPE, NON_PIPELINED) |
NVDEF(NVA0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE) |
NVDEF(NVA0B5, LAUNCH_DMA, SEMAPHORE_TYPE, NONE) |
NVDEF(NVA0B5, LAUNCH_DMA, INTERRUPT_TYPE, NONE) |
NVDEF(NVA0B5, LAUNCH_DMA, SRC_MEMORY_LAYOUT, PITCH) |
NVDEF(NVA0B5, LAUNCH_DMA, DST_MEMORY_LAYOUT, PITCH) |
NVDEF(NVA0B5, LAUNCH_DMA, MULTI_LINE_ENABLE, FALSE) |
NVDEF(NVA0B5, LAUNCH_DMA, REMAP_ENABLE, TRUE) |
NVDEF(NVA0B5, LAUNCH_DMA, BYPASS_L2, USE_PTE_SETTING));
return 0;
}