drm/amd/display: Add DCN316 resource and SMU clock manager
Add core DC implementation for DCN316. Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hansen Dsouza
Alex Deucher
parent
868f4357ed
commit
c477eaa6a7
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@ -36,6 +36,7 @@ DC_LIBS += dcn301
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DC_LIBS += dcn302
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DC_LIBS += dcn303
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DC_LIBS += dcn31
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DC_LIBS += dcn316
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endif
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DC_LIBS += dce120
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@ -153,4 +153,14 @@ CLK_MGR_DCN31 = dcn31_smu.o dcn31_clk_mgr.o
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AMD_DAL_CLK_MGR_DCN31 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn31/,$(CLK_MGR_DCN31))
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AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN31)
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###############################################################################
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# DCN316
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###############################################################################
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CLK_MGR_DCN316 = dcn316_smu.o dcn316_clk_mgr.o
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AMD_DAL_CLK_MGR_DCN316 = $(addprefix $(AMDDALPATH)/dc/clk_mgr/dcn316/,$(CLK_MGR_DCN316))
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AMD_DISPLAY_FILES += $(AMD_DAL_CLK_MGR_DCN316)
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endif
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@ -43,6 +43,7 @@
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#include "dcn30/dcn30_clk_mgr.h"
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#include "dcn301/vg_clk_mgr.h"
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#include "dcn31/dcn31_clk_mgr.h"
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#include "dcn316/dcn316_clk_mgr.h"
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int clk_mgr_helper_get_active_display_cnt(
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@ -278,8 +279,7 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
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return &clk_mgr->base.base;
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}
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break;
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case FAMILY_YELLOW_CARP:
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case AMDGPU_FAMILY_GC_10_3_7:{
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case FAMILY_YELLOW_CARP: {
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struct clk_mgr_dcn31 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
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if (clk_mgr == NULL) {
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@ -290,6 +290,17 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
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dcn31_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
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return &clk_mgr->base.base;
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}
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case AMDGPU_FAMILY_GC_10_3_7: {
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struct clk_mgr_dcn316 *clk_mgr = kzalloc(sizeof(*clk_mgr), GFP_KERNEL);
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if (clk_mgr == NULL) {
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BREAK_TO_DEBUGGER();
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return NULL;
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}
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dcn316_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
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return &clk_mgr->base.base;
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}
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#endif
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default:
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@ -323,10 +334,13 @@ void dc_destroy_clk_mgr(struct clk_mgr *clk_mgr_base)
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break;
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case FAMILY_YELLOW_CARP:
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case AMDGPU_FAMILY_GC_10_3_7:
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dcn31_clk_mgr_destroy(clk_mgr);
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break;
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case AMDGPU_FAMILY_GC_10_3_7:
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dcn316_clk_mgr_destroy(clk_mgr);
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break;
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default:
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break;
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}
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@ -0,0 +1,706 @@
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/*
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* Copyright 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "dccg.h"
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#include "clk_mgr_internal.h"
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// For dce12_get_dp_ref_freq_khz
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#include "dce100/dce_clk_mgr.h"
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// For dcn20_update_clocks_update_dpp_dto
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#include "dcn20/dcn20_clk_mgr.h"
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#include "dcn31/dcn31_clk_mgr.h"
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#include "dcn316_clk_mgr.h"
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#include "reg_helper.h"
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#include "core_types.h"
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#include "dcn316_smu.h"
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#include "dm_helpers.h"
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#include "dc_dmub_srv.h"
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#include "dc_link_dp.h"
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// DCN316 this is CLK1 instance
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#define MAX_INSTANCE 7
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#define MAX_SEGMENT 6
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struct IP_BASE_INSTANCE
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{
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unsigned int segment[MAX_SEGMENT];
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};
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struct IP_BASE
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{
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struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
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};
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static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } },
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{ { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } },
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{ { 0x00017000, 0x02402000, 0, 0, 0, 0 } },
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{ { 0x00017200, 0x02402400, 0, 0, 0, 0 } },
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{ { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } },
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{ { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } },
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{ { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } };
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#define regCLK1_CLK_PLL_REQ 0x0237
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#define regCLK1_CLK_PLL_REQ_BASE_IDX 0
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#define CLK1_CLK_PLL_REQ__FbMult_int__SHIFT 0x0
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#define CLK1_CLK_PLL_REQ__PllSpineDiv__SHIFT 0xc
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#define CLK1_CLK_PLL_REQ__FbMult_frac__SHIFT 0x10
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#define CLK1_CLK_PLL_REQ__FbMult_int_MASK 0x000001FFL
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#define CLK1_CLK_PLL_REQ__PllSpineDiv_MASK 0x0000F000L
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#define CLK1_CLK_PLL_REQ__FbMult_frac_MASK 0xFFFF0000L
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#define REG(reg_name) \
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(CLK_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
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#define TO_CLK_MGR_DCN316(clk_mgr)\
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container_of(clk_mgr, struct clk_mgr_dcn316, base)
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static int dcn316_get_active_display_cnt_wa(
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struct dc *dc,
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struct dc_state *context)
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{
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int i, display_count;
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bool tmds_present = false;
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display_count = 0;
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for (i = 0; i < context->stream_count; i++) {
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const struct dc_stream_state *stream = context->streams[i];
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if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A ||
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stream->signal == SIGNAL_TYPE_DVI_SINGLE_LINK ||
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stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK)
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tmds_present = true;
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}
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for (i = 0; i < dc->link_count; i++) {
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const struct dc_link *link = dc->links[i];
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/* abusing the fact that the dig and phy are coupled to see if the phy is enabled */
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if (link->link_enc && link->link_enc->funcs->is_dig_enabled &&
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link->link_enc->funcs->is_dig_enabled(link->link_enc))
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display_count++;
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}
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/* WA for hang on HDMI after display off back back on*/
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if (display_count == 0 && tmds_present)
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display_count = 1;
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return display_count;
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}
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static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, bool disable)
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{
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struct dc *dc = clk_mgr_base->ctx->dc;
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int i;
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for (i = 0; i < dc->res_pool->pipe_count; ++i) {
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struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
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if (pipe->top_pipe || pipe->prev_odm_pipe)
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continue;
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if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) {
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if (disable)
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pipe->stream_res.tg->funcs->immediate_disable_crtc(pipe->stream_res.tg);
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else
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pipe->stream_res.tg->funcs->enable_crtc(pipe->stream_res.tg);
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}
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}
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}
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static void dcn316_enable_pme_wa(struct clk_mgr *clk_mgr_base)
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{
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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dcn316_smu_enable_pme_wa(clk_mgr);
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}
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static void dcn316_update_clocks(struct clk_mgr *clk_mgr_base,
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struct dc_state *context,
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bool safe_to_lower)
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{
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union dmub_rb_cmd cmd;
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struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
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struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
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struct dc *dc = clk_mgr_base->ctx->dc;
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int display_count;
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bool update_dppclk = false;
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bool update_dispclk = false;
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bool dpp_clock_lowered = false;
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if (dc->work_arounds.skip_clock_update)
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return;
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/*
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* if it is safe to lower, but we are already in the lower state, we don't have to do anything
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* also if safe to lower is false, we just go in the higher state
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*/
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clk_mgr_base->clks.zstate_support = new_clocks->zstate_support;
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if (safe_to_lower) {
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if (clk_mgr_base->clks.dtbclk_en && !new_clocks->dtbclk_en) {
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dcn316_smu_set_dtbclk(clk_mgr, false);
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clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
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}
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/* check that we're not already in lower */
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if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) {
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display_count = dcn316_get_active_display_cnt_wa(dc, context);
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/* if we can go lower, go lower */
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if (display_count == 0) {
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union display_idle_optimization_u idle_info = { 0 };
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idle_info.idle_info.df_request_disabled = 1;
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idle_info.idle_info.phy_ref_clk_off = 1;
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// Todo DCN316 set this to 1 if any no issue
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idle_info.idle_info.s0i2_rdy = 0;
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dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
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/* update power state */
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clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER;
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}
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}
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} else {
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if (!clk_mgr_base->clks.dtbclk_en && new_clocks->dtbclk_en) {
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dcn316_smu_set_dtbclk(clk_mgr, true);
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clk_mgr_base->clks.dtbclk_en = new_clocks->dtbclk_en;
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}
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/* check that we're not already in D0 */
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if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) {
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union display_idle_optimization_u idle_info = { 0 };
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dcn316_smu_set_display_idle_optimization(clk_mgr, idle_info.data);
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/* update power state */
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clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE;
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}
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}
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if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
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clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
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dcn316_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
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}
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if (should_set_clock(safe_to_lower,
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new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
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clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
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dcn316_smu_set_min_deep_sleep_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_deep_sleep_khz);
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}
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// workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
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if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
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if (new_clocks->dppclk_khz < 100000)
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new_clocks->dppclk_khz = 100000;
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if (new_clocks->dispclk_khz < 100000)
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new_clocks->dispclk_khz = 100000;
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}
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if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
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if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
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dpp_clock_lowered = true;
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clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
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update_dppclk = true;
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}
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if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
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dcn316_disable_otg_wa(clk_mgr_base, true);
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clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
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dcn316_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz);
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dcn316_disable_otg_wa(clk_mgr_base, false);
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update_dispclk = true;
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}
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if (dpp_clock_lowered) {
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// increase per DPP DTO before lowering global dppclk
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dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
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dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
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} else {
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// increase global DPPCLK before lowering per DPP DTO
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if (update_dppclk || update_dispclk)
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dcn316_smu_set_dppclk(clk_mgr, clk_mgr_base->clks.dppclk_khz);
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// always update dtos unless clock is lowered and not safe to lower
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if (new_clocks->dppclk_khz >= dc->current_state->bw_ctx.bw.dcn.clk.dppclk_khz)
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dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
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}
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// notify DMCUB of latest clocks
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memset(&cmd, 0, sizeof(cmd));
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cmd.notify_clocks.header.type = DMUB_CMD__CLK_MGR;
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cmd.notify_clocks.header.sub_type = DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS;
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cmd.notify_clocks.clocks.dcfclk_khz = clk_mgr_base->clks.dcfclk_khz;
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cmd.notify_clocks.clocks.dcfclk_deep_sleep_khz =
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clk_mgr_base->clks.dcfclk_deep_sleep_khz;
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cmd.notify_clocks.clocks.dispclk_khz = clk_mgr_base->clks.dispclk_khz;
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cmd.notify_clocks.clocks.dppclk_khz = clk_mgr_base->clks.dppclk_khz;
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dc_dmub_srv_cmd_queue(dc->ctx->dmub_srv, &cmd);
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dc_dmub_srv_cmd_execute(dc->ctx->dmub_srv);
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dc_dmub_srv_wait_idle(dc->ctx->dmub_srv);
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}
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static void dcn316_dump_clk_registers(struct clk_state_registers_and_bypass *regs_and_bypass,
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struct clk_mgr *clk_mgr_base, struct clk_log_info *log_info)
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{
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return;
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}
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static struct clk_bw_params dcn316_bw_params = {
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.vram_type = Ddr4MemType,
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.num_channels = 1,
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.clk_table = {
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.num_entries = 5,
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},
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};
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static struct wm_table ddr4_wm_table = {
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.entries = {
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{
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.wm_inst = WM_A,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 6.09,
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.sr_enter_plus_exit_time_us = 7.14,
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.valid = true,
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},
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{
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
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.sr_enter_plus_exit_time_us = 11.48,
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.valid = true,
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},
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{
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
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.sr_enter_plus_exit_time_us = 11.48,
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.valid = true,
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},
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{
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
|
||||
.sr_enter_plus_exit_time_us = 11.48,
|
||||
.valid = true,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
static struct wm_table lpddr5_wm_table = {
|
||||
.entries = {
|
||||
{
|
||||
.wm_inst = WM_A,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.65333,
|
||||
.sr_exit_time_us = 11.5,
|
||||
.sr_enter_plus_exit_time_us = 14.5,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_B,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.65333,
|
||||
.sr_exit_time_us = 11.5,
|
||||
.sr_enter_plus_exit_time_us = 14.5,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_C,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.65333,
|
||||
.sr_exit_time_us = 11.5,
|
||||
.sr_enter_plus_exit_time_us = 14.5,
|
||||
.valid = true,
|
||||
},
|
||||
{
|
||||
.wm_inst = WM_D,
|
||||
.wm_type = WM_TYPE_PSTATE_CHG,
|
||||
.pstate_latency_us = 11.65333,
|
||||
.sr_exit_time_us = 11.5,
|
||||
.sr_enter_plus_exit_time_us = 14.5,
|
||||
.valid = true,
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
static DpmClocks_316_t dummy_clocks;
|
||||
|
||||
static struct dcn316_watermarks dummy_wms = { 0 };
|
||||
|
||||
static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
|
||||
{
|
||||
int i, num_valid_sets;
|
||||
|
||||
num_valid_sets = 0;
|
||||
|
||||
for (i = 0; i < WM_SET_COUNT; i++) {
|
||||
/* skip empty entries, the smu array has no holes*/
|
||||
if (!bw_params->wm_table.entries[i].valid)
|
||||
continue;
|
||||
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
|
||||
/* We will not select WM based on fclk, so leave it as unconstrained */
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
|
||||
|
||||
if (table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType == WM_TYPE_PSTATE_CHG) {
|
||||
if (i == 0)
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk = 0;
|
||||
else {
|
||||
/* add 1 to make it non-overlapping with next lvl */
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
|
||||
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
|
||||
}
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
|
||||
bw_params->clk_table.entries[i].dcfclk_mhz;
|
||||
|
||||
} else {
|
||||
/* unconstrained for memory retraining */
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
|
||||
|
||||
/* Modify previous watermark range to cover up to max */
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
|
||||
}
|
||||
num_valid_sets++;
|
||||
}
|
||||
|
||||
ASSERT(num_valid_sets != 0); /* Must have at least one set of valid watermarks */
|
||||
|
||||
/* modify the min and max to make sure we cover the whole range*/
|
||||
table->WatermarkRow[WM_DCFCLK][0].MinMclk = 0;
|
||||
table->WatermarkRow[WM_DCFCLK][0].MinClock = 0;
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxMclk = 0xFFFF;
|
||||
table->WatermarkRow[WM_DCFCLK][num_valid_sets - 1].MaxClock = 0xFFFF;
|
||||
|
||||
/* This is for writeback only, does not matter currently as no writeback support*/
|
||||
table->WatermarkRow[WM_SOCCLK][0].WmSetting = WM_A;
|
||||
table->WatermarkRow[WM_SOCCLK][0].MinClock = 0;
|
||||
table->WatermarkRow[WM_SOCCLK][0].MaxClock = 0xFFFF;
|
||||
table->WatermarkRow[WM_SOCCLK][0].MinMclk = 0;
|
||||
table->WatermarkRow[WM_SOCCLK][0].MaxMclk = 0xFFFF;
|
||||
}
|
||||
|
||||
static void dcn316_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
|
||||
{
|
||||
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
|
||||
struct clk_mgr_dcn316 *clk_mgr_dcn316 = TO_CLK_MGR_DCN316(clk_mgr);
|
||||
struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set;
|
||||
|
||||
if (!clk_mgr->smu_ver)
|
||||
return;
|
||||
|
||||
if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0)
|
||||
return;
|
||||
|
||||
memset(table, 0, sizeof(*table));
|
||||
|
||||
dcn316_build_watermark_ranges(clk_mgr_base->bw_params, table);
|
||||
|
||||
dcn316_smu_set_dram_addr_high(clk_mgr,
|
||||
clk_mgr_dcn316->smu_wm_set.mc_address.high_part);
|
||||
dcn316_smu_set_dram_addr_low(clk_mgr,
|
||||
clk_mgr_dcn316->smu_wm_set.mc_address.low_part);
|
||||
dcn316_smu_transfer_wm_table_dram_2_smu(clk_mgr);
|
||||
}
|
||||
|
||||
static void dcn316_get_dpm_table_from_smu(struct clk_mgr_internal *clk_mgr,
|
||||
struct dcn316_smu_dpm_clks *smu_dpm_clks)
|
||||
{
|
||||
DpmClocks_316_t *table = smu_dpm_clks->dpm_clks;
|
||||
|
||||
if (!clk_mgr->smu_ver)
|
||||
return;
|
||||
|
||||
if (!table || smu_dpm_clks->mc_address.quad_part == 0)
|
||||
return;
|
||||
|
||||
memset(table, 0, sizeof(*table));
|
||||
|
||||
dcn316_smu_set_dram_addr_high(clk_mgr,
|
||||
smu_dpm_clks->mc_address.high_part);
|
||||
dcn316_smu_set_dram_addr_low(clk_mgr,
|
||||
smu_dpm_clks->mc_address.low_part);
|
||||
dcn316_smu_transfer_dpm_table_smu_2_dram(clk_mgr);
|
||||
}
|
||||
|
||||
static uint32_t find_max_clk_value(const uint32_t clocks[], uint32_t num_clocks)
|
||||
{
|
||||
uint32_t max = 0;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < num_clocks; ++i) {
|
||||
if (clocks[i] > max)
|
||||
max = clocks[i];
|
||||
}
|
||||
|
||||
return max;
|
||||
}
|
||||
|
||||
static unsigned int find_clk_for_voltage(
|
||||
const DpmClocks_316_t *clock_table,
|
||||
const uint32_t clocks[],
|
||||
unsigned int voltage)
|
||||
{
|
||||
int i;
|
||||
int max_voltage = 0;
|
||||
int clock = 0;
|
||||
|
||||
for (i = 0; i < NUM_SOC_VOLTAGE_LEVELS; i++) {
|
||||
if (clock_table->SocVoltage[i] == voltage) {
|
||||
return clocks[i];
|
||||
} else if (clock_table->SocVoltage[i] >= max_voltage &&
|
||||
clock_table->SocVoltage[i] < voltage) {
|
||||
max_voltage = clock_table->SocVoltage[i];
|
||||
clock = clocks[i];
|
||||
}
|
||||
}
|
||||
|
||||
ASSERT(clock);
|
||||
return clock;
|
||||
}
|
||||
|
||||
void dcn316_clk_mgr_helper_populate_bw_params(
|
||||
struct clk_mgr_internal *clk_mgr,
|
||||
struct integrated_info *bios_info,
|
||||
const DpmClocks_316_t *clock_table)
|
||||
{
|
||||
int i, j;
|
||||
struct clk_bw_params *bw_params = clk_mgr->base.bw_params;
|
||||
uint32_t max_dispclk = 0, max_dppclk = 0;
|
||||
|
||||
j = -1;
|
||||
|
||||
ASSERT(NUM_DF_PSTATE_LEVELS <= MAX_NUM_DPM_LVL);
|
||||
|
||||
/* Find lowest DPM, FCLK is filled in reverse order*/
|
||||
|
||||
for (i = NUM_DF_PSTATE_LEVELS - 1; i >= 0; i--) {
|
||||
if (clock_table->DfPstateTable[i].FClk != 0) {
|
||||
j = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (j == -1) {
|
||||
/* clock table is all 0s, just use our own hardcode */
|
||||
ASSERT(0);
|
||||
return;
|
||||
}
|
||||
|
||||
bw_params->clk_table.num_entries = j + 1;
|
||||
|
||||
/* dispclk and dppclk can be max at any voltage, same number of levels for both */
|
||||
if (clock_table->NumDispClkLevelsEnabled <= NUM_DISPCLK_DPM_LEVELS &&
|
||||
clock_table->NumDispClkLevelsEnabled <= NUM_DPPCLK_DPM_LEVELS) {
|
||||
max_dispclk = find_max_clk_value(clock_table->DispClocks, clock_table->NumDispClkLevelsEnabled);
|
||||
max_dppclk = find_max_clk_value(clock_table->DppClocks, clock_table->NumDispClkLevelsEnabled);
|
||||
} else {
|
||||
ASSERT(0);
|
||||
}
|
||||
|
||||
for (i = 0; i < bw_params->clk_table.num_entries; i++, j--) {
|
||||
int temp;
|
||||
|
||||
bw_params->clk_table.entries[i].fclk_mhz = clock_table->DfPstateTable[j].FClk;
|
||||
bw_params->clk_table.entries[i].memclk_mhz = clock_table->DfPstateTable[j].MemClk;
|
||||
bw_params->clk_table.entries[i].voltage = clock_table->DfPstateTable[j].Voltage;
|
||||
bw_params->clk_table.entries[i].wck_ratio = 1;
|
||||
temp = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
|
||||
if (temp)
|
||||
bw_params->clk_table.entries[i].dcfclk_mhz = temp;
|
||||
temp = find_clk_for_voltage(clock_table, clock_table->SocClocks, clock_table->DfPstateTable[j].Voltage);
|
||||
if (temp)
|
||||
bw_params->clk_table.entries[i].socclk_mhz = temp;
|
||||
bw_params->clk_table.entries[i].dispclk_mhz = max_dispclk;
|
||||
bw_params->clk_table.entries[i].dppclk_mhz = max_dppclk;
|
||||
}
|
||||
|
||||
bw_params->vram_type = bios_info->memory_type;
|
||||
bw_params->num_channels = bios_info->ma_channel_number;
|
||||
|
||||
for (i = 0; i < WM_SET_COUNT; i++) {
|
||||
bw_params->wm_table.entries[i].wm_inst = i;
|
||||
|
||||
if (i >= bw_params->clk_table.num_entries) {
|
||||
bw_params->wm_table.entries[i].valid = false;
|
||||
continue;
|
||||
}
|
||||
|
||||
bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG;
|
||||
bw_params->wm_table.entries[i].valid = true;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
static struct clk_mgr_funcs dcn316_funcs = {
|
||||
.enable_pme_wa = dcn316_enable_pme_wa,
|
||||
.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
|
||||
.update_clocks = dcn316_update_clocks,
|
||||
.init_clocks = dcn31_init_clocks,
|
||||
.are_clock_states_equal = dcn31_are_clock_states_equal,
|
||||
.notify_wm_ranges = dcn316_notify_wm_ranges
|
||||
};
|
||||
extern struct clk_mgr_funcs dcn3_fpga_funcs;
|
||||
|
||||
static int get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
/* get FbMult value */
|
||||
struct fixed31_32 pll_req;
|
||||
unsigned int fbmult_frac_val = 0;
|
||||
unsigned int fbmult_int_val = 0;
|
||||
|
||||
/*
|
||||
* Register value of fbmult is in 8.16 format, we are converting to 31.32
|
||||
* to leverage the fix point operations available in driver
|
||||
*/
|
||||
|
||||
REG_GET(CLK1_CLK_PLL_REQ, FbMult_frac, &fbmult_frac_val); /* 16 bit fractional part*/
|
||||
REG_GET(CLK1_CLK_PLL_REQ, FbMult_int, &fbmult_int_val); /* 8 bit integer part */
|
||||
|
||||
pll_req = dc_fixpt_from_int(fbmult_int_val);
|
||||
|
||||
/*
|
||||
* since fractional part is only 16 bit in register definition but is 32 bit
|
||||
* in our fix point definiton, need to shift left by 16 to obtain correct value
|
||||
*/
|
||||
pll_req.value |= fbmult_frac_val << 16;
|
||||
|
||||
/* multiply by REFCLK period */
|
||||
pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
|
||||
|
||||
/* integer part is now VCO frequency in kHz */
|
||||
return dc_fixpt_floor(pll_req);
|
||||
}
|
||||
|
||||
void dcn316_clk_mgr_construct(
|
||||
struct dc_context *ctx,
|
||||
struct clk_mgr_dcn316 *clk_mgr,
|
||||
struct pp_smu_funcs *pp_smu,
|
||||
struct dccg *dccg)
|
||||
{
|
||||
struct dcn316_smu_dpm_clks smu_dpm_clks = { 0 };
|
||||
|
||||
clk_mgr->base.base.ctx = ctx;
|
||||
clk_mgr->base.base.funcs = &dcn316_funcs;
|
||||
|
||||
clk_mgr->base.pp_smu = pp_smu;
|
||||
|
||||
clk_mgr->base.dccg = dccg;
|
||||
clk_mgr->base.dfs_bypass_disp_clk = 0;
|
||||
|
||||
clk_mgr->base.dprefclk_ss_percentage = 0;
|
||||
clk_mgr->base.dprefclk_ss_divider = 1000;
|
||||
clk_mgr->base.ss_on_dprefclk = false;
|
||||
clk_mgr->base.dfs_ref_freq_khz = 48000;
|
||||
|
||||
clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem(
|
||||
clk_mgr->base.base.ctx,
|
||||
DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
|
||||
sizeof(struct dcn316_watermarks),
|
||||
&clk_mgr->smu_wm_set.mc_address.quad_part);
|
||||
|
||||
if (!clk_mgr->smu_wm_set.wm_set) {
|
||||
clk_mgr->smu_wm_set.wm_set = &dummy_wms;
|
||||
clk_mgr->smu_wm_set.mc_address.quad_part = 0;
|
||||
}
|
||||
ASSERT(clk_mgr->smu_wm_set.wm_set);
|
||||
|
||||
smu_dpm_clks.dpm_clks = (DpmClocks_316_t *)dm_helpers_allocate_gpu_mem(
|
||||
clk_mgr->base.base.ctx,
|
||||
DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
|
||||
sizeof(DpmClocks_316_t),
|
||||
&smu_dpm_clks.mc_address.quad_part);
|
||||
|
||||
if (smu_dpm_clks.dpm_clks == NULL) {
|
||||
smu_dpm_clks.dpm_clks = &dummy_clocks;
|
||||
smu_dpm_clks.mc_address.quad_part = 0;
|
||||
}
|
||||
|
||||
ASSERT(smu_dpm_clks.dpm_clks);
|
||||
|
||||
if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
|
||||
clk_mgr->base.base.funcs = &dcn3_fpga_funcs;
|
||||
clk_mgr->base.base.dentist_vco_freq_khz = 2500000;
|
||||
} else {
|
||||
struct clk_log_info log_info = {0};
|
||||
|
||||
clk_mgr->base.smu_ver = dcn316_smu_get_smu_version(&clk_mgr->base);
|
||||
|
||||
if (clk_mgr->base.smu_ver > 0)
|
||||
clk_mgr->base.smu_present = true;
|
||||
|
||||
// Skip this for now as it did not work on DCN315, renable during bring up
|
||||
clk_mgr->base.base.dentist_vco_freq_khz = get_vco_frequency_from_reg(&clk_mgr->base);
|
||||
|
||||
/* in case we don't get a value from the register, use default */
|
||||
if (clk_mgr->base.base.dentist_vco_freq_khz == 0)
|
||||
clk_mgr->base.base.dentist_vco_freq_khz = 2500000; /* 2400MHz */
|
||||
|
||||
|
||||
if (ctx->dc_bios->integrated_info->memory_type == LpDdr5MemType) {
|
||||
dcn316_bw_params.wm_table = lpddr5_wm_table;
|
||||
} else {
|
||||
dcn316_bw_params.wm_table = ddr4_wm_table;
|
||||
}
|
||||
/* Saved clocks configured at boot for debug purposes */
|
||||
dcn316_dump_clk_registers(&clk_mgr->base.base.boot_snapshot, &clk_mgr->base.base, &log_info);
|
||||
|
||||
}
|
||||
|
||||
clk_mgr->base.base.dprefclk_khz = 600000;
|
||||
clk_mgr->base.dccg->ref_dtbclk_khz = 600000;
|
||||
dce_clock_read_ss_info(&clk_mgr->base);
|
||||
|
||||
clk_mgr->base.base.bw_params = &dcn316_bw_params;
|
||||
|
||||
if (clk_mgr->base.base.ctx->dc->debug.pstate_enabled) {
|
||||
dcn316_get_dpm_table_from_smu(&clk_mgr->base, &smu_dpm_clks);
|
||||
|
||||
if (ctx->dc_bios && ctx->dc_bios->integrated_info) {
|
||||
dcn316_clk_mgr_helper_populate_bw_params(
|
||||
&clk_mgr->base,
|
||||
ctx->dc_bios->integrated_info,
|
||||
smu_dpm_clks.dpm_clks);
|
||||
}
|
||||
}
|
||||
|
||||
if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0)
|
||||
dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
|
||||
smu_dpm_clks.dpm_clks);
|
||||
}
|
||||
|
||||
void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
|
||||
{
|
||||
struct clk_mgr_dcn316 *clk_mgr = TO_CLK_MGR_DCN316(clk_mgr_int);
|
||||
|
||||
if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
|
||||
dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
|
||||
clk_mgr->smu_wm_set.wm_set);
|
||||
}
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __DCN316_CLK_MGR_H__
|
||||
#define __DCN316_CLK_MGR_H__
|
||||
#include "clk_mgr_internal.h"
|
||||
|
||||
struct dcn316_watermarks;
|
||||
|
||||
struct dcn316_smu_watermark_set {
|
||||
struct dcn316_watermarks *wm_set;
|
||||
union large_integer mc_address;
|
||||
};
|
||||
|
||||
struct clk_mgr_dcn316 {
|
||||
struct clk_mgr_internal base;
|
||||
struct dcn316_smu_watermark_set smu_wm_set;
|
||||
};
|
||||
|
||||
void dcn316_clk_mgr_construct(struct dc_context *ctx,
|
||||
struct clk_mgr_dcn316 *clk_mgr,
|
||||
struct pp_smu_funcs *pp_smu,
|
||||
struct dccg *dccg);
|
||||
|
||||
void dcn316_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int);
|
||||
|
||||
#endif //__DCN316_CLK_MGR_H__
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#include "core_types.h"
|
||||
#include "clk_mgr_internal.h"
|
||||
#include "reg_helper.h"
|
||||
#include "dm_helpers.h"
|
||||
#include "dcn316_smu.h"
|
||||
#include "mp/mp_13_0_8_offset.h"
|
||||
#include "mp/mp_13_0_8_sh_mask.h"
|
||||
|
||||
#define MAX_INSTANCE 7
|
||||
#define MAX_SEGMENT 6
|
||||
|
||||
struct IP_BASE_INSTANCE
|
||||
{
|
||||
unsigned int segment[MAX_SEGMENT];
|
||||
};
|
||||
|
||||
struct IP_BASE
|
||||
{
|
||||
struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
|
||||
};
|
||||
|
||||
static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x00DC0000, 0x00E00000, 0x00E40000, 0x0243FC00, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0 } } } };
|
||||
|
||||
#define REG(reg_name) \
|
||||
(MP0_BASE.instance[0].segment[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
|
||||
|
||||
#define FN(reg_name, field) \
|
||||
FD(reg_name##__##field)
|
||||
|
||||
#define VBIOSSMC_MSG_TestMessage 0x01 ///< To check if PMFW is alive and responding. Requirement specified by PMFW team
|
||||
#define VBIOSSMC_MSG_GetPmfwVersion 0x02 ///< Get PMFW version
|
||||
#define VBIOSSMC_MSG_Spare0 0x03 ///< Spare0
|
||||
#define VBIOSSMC_MSG_SetDispclkFreq 0x04 ///< Set display clock frequency in MHZ
|
||||
#define VBIOSSMC_MSG_Spare1 0x05 ///< Spare1
|
||||
#define VBIOSSMC_MSG_SetDppclkFreq 0x06 ///< Set DPP clock frequency in MHZ
|
||||
#define VBIOSSMC_MSG_SetHardMinDcfclkByFreq 0x07 ///< Set DCF clock frequency hard min in MHZ
|
||||
#define VBIOSSMC_MSG_SetMinDeepSleepDcfclk 0x08 ///< Set DCF clock minimum frequency in deep sleep in MHZ
|
||||
#define VBIOSSMC_MSG_SetPhyclkVoltageByFreq 0x09 ///< Set display phy clock frequency in MHZ in case VMIN does not support phy frequency
|
||||
#define VBIOSSMC_MSG_GetFclkFrequency 0x0A ///< Get FCLK frequency, return frequemcy in MHZ
|
||||
#define VBIOSSMC_MSG_SetDisplayCount 0x0B ///< Inform PMFW of number of display connected
|
||||
#define VBIOSSMC_MSG_SPARE 0x0C ///< SPARE
|
||||
#define VBIOSSMC_MSG_UpdatePmeRestore 0x0D ///< To ask PMFW to write into Azalia for PME wake up event
|
||||
#define VBIOSSMC_MSG_SetVbiosDramAddrHigh 0x0E ///< Set DRAM address high 32 bits for WM table transfer
|
||||
#define VBIOSSMC_MSG_SetVbiosDramAddrLow 0x0F ///< Set DRAM address low 32 bits for WM table transfer
|
||||
#define VBIOSSMC_MSG_TransferTableSmu2Dram 0x10 ///< Transfer table from PMFW SRAM to system DRAM
|
||||
#define VBIOSSMC_MSG_TransferTableDram2Smu 0x11 ///< Transfer table from system DRAM to PMFW
|
||||
#define VBIOSSMC_MSG_SetDisplayIdleOptimizations 0x12 ///< Set Idle state optimization for display off
|
||||
#define VBIOSSMC_MSG_GetDprefclkFreq 0x13 ///< Get DPREF clock frequency. Return in MHZ
|
||||
#define VBIOSSMC_MSG_GetDtbclkFreq 0x14 ///< Get DPREF clock frequency. Return in MHZ
|
||||
#define VBIOSSMC_MSG_SetDtbclkFreq 0x15 ///< Inform PMFW to turn on/off DTB clock arg = 1, turn DTB clock on 600MHz/ arg = 0 turn DTB clock off
|
||||
#define VBIOSSMC_Message_Count 0x16 ///< Total number of VBIS and DAL messages
|
||||
|
||||
#define VBIOSSMC_Status_BUSY 0x0
|
||||
#define VBIOSSMC_Result_OK 0x01 ///< Message Response OK
|
||||
#define VBIOSSMC_Result_Failed 0xFF ///< Message Response Failed
|
||||
#define VBIOSSMC_Result_UnknownCmd 0xFE ///< Message Response Unknown Command
|
||||
#define VBIOSSMC_Result_CmdRejectedPrereq 0xFD ///< Message Response Command Failed Prerequisite
|
||||
#define VBIOSSMC_Result_CmdRejectedBusy 0xFC ///< Message Response Command Rejected due to PMFW is busy. Sender should retry sending this message
|
||||
|
||||
/*
|
||||
* Function to be used instead of REG_WAIT macro because the wait ends when
|
||||
* the register is NOT EQUAL to zero, and because the translation in msg_if.h
|
||||
* won't work with REG_WAIT.
|
||||
*/
|
||||
static uint32_t dcn316_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
|
||||
{
|
||||
uint32_t res_val = VBIOSSMC_Status_BUSY;
|
||||
|
||||
do {
|
||||
res_val = REG_READ(MP1_SMN_C2PMSG_91);
|
||||
if (res_val != VBIOSSMC_Status_BUSY)
|
||||
break;
|
||||
|
||||
if (delay_us >= 1000)
|
||||
msleep(delay_us/1000);
|
||||
else if (delay_us > 0)
|
||||
udelay(delay_us);
|
||||
} while (max_retries--);
|
||||
|
||||
return res_val;
|
||||
}
|
||||
|
||||
int dcn316_smu_send_msg_with_param(
|
||||
struct clk_mgr_internal *clk_mgr,
|
||||
unsigned int msg_id, unsigned int param)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);
|
||||
ASSERT(result == VBIOSSMC_Result_OK);
|
||||
|
||||
if (result == VBIOSSMC_Status_BUSY) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* First clear response register */
|
||||
REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
|
||||
|
||||
/* Set the parameter register for the SMU message, unit is Mhz */
|
||||
REG_WRITE(MP1_SMN_C2PMSG_83, param);
|
||||
|
||||
/* Trigger the message transaction by writing the message ID */
|
||||
REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
|
||||
|
||||
result = dcn316_smu_wait_for_response(clk_mgr, 10, 200000);
|
||||
|
||||
if (result == VBIOSSMC_Status_BUSY) {
|
||||
ASSERT(0);
|
||||
dm_helpers_smu_timeout(CTX, msg_id, param, 10 * 200000);
|
||||
}
|
||||
|
||||
return REG_READ(MP1_SMN_C2PMSG_83);
|
||||
}
|
||||
|
||||
int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
return dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_GetPmfwVersion,
|
||||
0);
|
||||
}
|
||||
|
||||
|
||||
int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
|
||||
{
|
||||
int actual_dispclk_set_mhz = -1;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return requested_dispclk_khz;
|
||||
|
||||
/* Unit of SMU msg parameter is Mhz */
|
||||
actual_dispclk_set_mhz = dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetDispclkFreq,
|
||||
khz_to_mhz_ceil(requested_dispclk_khz));
|
||||
|
||||
return actual_dispclk_set_mhz * 1000;
|
||||
}
|
||||
|
||||
int dcn316_smu_set_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz)
|
||||
{
|
||||
int actual_phypclk_set_mhz = -1;
|
||||
|
||||
if (!clk_mgr->smu_present && requested_phyclk_khz)
|
||||
return requested_phyclk_khz;
|
||||
|
||||
/* Unit of SMU msg parameter is Mhz */
|
||||
actual_phypclk_set_mhz = dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetPhyclkVoltageByFreq,
|
||||
khz_to_mhz_ceil(requested_phyclk_khz));
|
||||
|
||||
return actual_phypclk_set_mhz * 1000;
|
||||
}
|
||||
|
||||
int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz)
|
||||
{
|
||||
int actual_dcfclk_set_mhz = -1;
|
||||
|
||||
if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
|
||||
return -1;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return requested_dcfclk_khz;
|
||||
|
||||
actual_dcfclk_set_mhz = dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetHardMinDcfclkByFreq,
|
||||
khz_to_mhz_ceil(requested_dcfclk_khz));
|
||||
|
||||
return actual_dcfclk_set_mhz * 1000;
|
||||
}
|
||||
|
||||
int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz)
|
||||
{
|
||||
int actual_min_ds_dcfclk_mhz = -1;
|
||||
|
||||
if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
|
||||
return -1;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return requested_min_ds_dcfclk_khz;
|
||||
|
||||
actual_min_ds_dcfclk_mhz = dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetMinDeepSleepDcfclk,
|
||||
khz_to_mhz_ceil(requested_min_ds_dcfclk_khz));
|
||||
|
||||
return actual_min_ds_dcfclk_mhz * 1000;
|
||||
}
|
||||
|
||||
int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz)
|
||||
{
|
||||
int actual_dppclk_set_mhz = -1;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return requested_dpp_khz;
|
||||
|
||||
actual_dppclk_set_mhz = dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetDppclkFreq,
|
||||
khz_to_mhz_ceil(requested_dpp_khz));
|
||||
|
||||
return actual_dppclk_set_mhz * 1000;
|
||||
}
|
||||
|
||||
void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info)
|
||||
{
|
||||
if (!clk_mgr->base.ctx->dc->debug.pstate_enabled)
|
||||
return;
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
//TODO: Work with smu team to define optimization options.
|
||||
dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
|
||||
idle_info);
|
||||
}
|
||||
|
||||
void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable)
|
||||
{
|
||||
union display_idle_optimization_u idle_info = { 0 };
|
||||
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
if (enable) {
|
||||
idle_info.idle_info.df_request_disabled = 1;
|
||||
idle_info.idle_info.phy_ref_clk_off = 1;
|
||||
}
|
||||
|
||||
dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetDisplayIdleOptimizations,
|
||||
idle_info.data);
|
||||
}
|
||||
|
||||
void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn316_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_SetVbiosDramAddrHigh, addr_high);
|
||||
}
|
||||
|
||||
void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn316_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_SetVbiosDramAddrLow, addr_low);
|
||||
}
|
||||
|
||||
void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn316_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_TransferTableSmu2Dram, TABLE_DPMCLOCKS);
|
||||
}
|
||||
|
||||
void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn316_smu_send_msg_with_param(clk_mgr,
|
||||
VBIOSSMC_MSG_TransferTableDram2Smu, TABLE_WATERMARKS);
|
||||
}
|
||||
|
||||
void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_UpdatePmeRestore,
|
||||
0);
|
||||
}
|
||||
|
||||
/* Arg = 1: Turn DTB on; 0: Turn DTB CLK OFF. when it is on, it is 600MHZ */
|
||||
void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
|
||||
{
|
||||
if (!clk_mgr->smu_present)
|
||||
return;
|
||||
|
||||
dcn316_smu_send_msg_with_param(
|
||||
clk_mgr,
|
||||
VBIOSSMC_MSG_SetDtbclkFreq,
|
||||
enable);
|
||||
}
|
||||
|
|
@ -0,0 +1,128 @@
|
|||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef DAL_DC_316_SMU_H_
|
||||
#define DAL_DC_316_SMU_H_
|
||||
#include "os_types.h"
|
||||
|
||||
#define PMFW_DRIVER_IF_VERSION 4
|
||||
|
||||
#define NUM_DCFCLK_DPM_LEVELS 8
|
||||
#define NUM_DISPCLK_DPM_LEVELS 8
|
||||
#define NUM_DPPCLK_DPM_LEVELS 8
|
||||
#define NUM_SOCCLK_DPM_LEVELS 8
|
||||
#define NUM_VCN_DPM_LEVELS 8
|
||||
#define NUM_SOC_VOLTAGE_LEVELS 8
|
||||
#define NUM_DF_PSTATE_LEVELS 4
|
||||
|
||||
typedef struct {
|
||||
uint16_t MinClock; // This is either DCFCLK or SOCCLK (in MHz)
|
||||
uint16_t MaxClock; // This is either DCFCLK or SOCCLK (in MHz)
|
||||
uint16_t MinMclk;
|
||||
uint16_t MaxMclk;
|
||||
uint8_t WmSetting;
|
||||
uint8_t WmType; // Used for normal pstate change or memory retraining
|
||||
uint8_t Padding[2];
|
||||
} WatermarkRowGeneric_t;
|
||||
|
||||
#define NUM_WM_RANGES 4
|
||||
#define WM_PSTATE_CHG 0
|
||||
#define WM_RETRAINING 1
|
||||
|
||||
typedef enum {
|
||||
WM_SOCCLK = 0,
|
||||
WM_DCFCLK,
|
||||
WM_COUNT,
|
||||
} WM_CLOCK_e;
|
||||
|
||||
typedef struct {
|
||||
uint32_t FClk;
|
||||
uint32_t MemClk;
|
||||
uint32_t Voltage;
|
||||
} DfPstateTable_t;
|
||||
|
||||
//Freq in MHz
|
||||
//Voltage in milli volts with 2 fractional bits
|
||||
typedef struct {
|
||||
uint32_t DcfClocks[NUM_DCFCLK_DPM_LEVELS];
|
||||
uint32_t DispClocks[NUM_DISPCLK_DPM_LEVELS];
|
||||
uint32_t DppClocks[NUM_DPPCLK_DPM_LEVELS];
|
||||
uint32_t SocClocks[NUM_SOCCLK_DPM_LEVELS];
|
||||
uint32_t VClocks[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t DClocks[NUM_VCN_DPM_LEVELS];
|
||||
uint32_t SocVoltage[NUM_SOC_VOLTAGE_LEVELS];
|
||||
DfPstateTable_t DfPstateTable[NUM_DF_PSTATE_LEVELS];
|
||||
uint8_t NumDcfClkLevelsEnabled;
|
||||
uint8_t NumDispClkLevelsEnabled; //Applies to both Dispclk and Dppclk
|
||||
uint8_t NumSocClkLevelsEnabled;
|
||||
uint8_t VcnClkLevelsEnabled; //Applies to both Vclk and Dclk
|
||||
uint8_t NumDfPstatesEnabled;
|
||||
uint8_t spare[3];
|
||||
uint32_t MinGfxClk;
|
||||
uint32_t MaxGfxClk;
|
||||
} DpmClocks_316_t;
|
||||
|
||||
struct dcn316_watermarks {
|
||||
// Watermarks
|
||||
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
|
||||
uint32_t MmHubPadding[7]; // SMU internal use
|
||||
};
|
||||
|
||||
struct dcn316_smu_dpm_clks {
|
||||
DpmClocks_316_t *dpm_clks;
|
||||
union large_integer mc_address;
|
||||
};
|
||||
|
||||
#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
|
||||
#define TABLE_DPMCLOCKS 4 // Called by Driver and VBIOS
|
||||
|
||||
struct display_idle_optimization {
|
||||
unsigned int df_request_disabled : 1;
|
||||
unsigned int phy_ref_clk_off : 1;
|
||||
unsigned int s0i2_rdy : 1;
|
||||
unsigned int reserved : 29;
|
||||
};
|
||||
|
||||
union display_idle_optimization_u {
|
||||
struct display_idle_optimization idle_info;
|
||||
uint32_t data;
|
||||
};
|
||||
|
||||
int dcn316_smu_get_smu_version(struct clk_mgr_internal *clk_mgr);
|
||||
int dcn316_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz);
|
||||
int dcn316_smu_set_hard_min_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_dcfclk_khz);
|
||||
int dcn316_smu_set_min_deep_sleep_dcfclk(struct clk_mgr_internal *clk_mgr, int requested_min_ds_dcfclk_khz);
|
||||
int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
|
||||
void dcn316_smu_set_display_idle_optimization(struct clk_mgr_internal *clk_mgr, uint32_t idle_info);
|
||||
void dcn316_smu_enable_phy_refclk_pwrdwn(struct clk_mgr_internal *clk_mgr, bool enable);
|
||||
void dcn316_smu_set_dram_addr_high(struct clk_mgr_internal *clk_mgr, uint32_t addr_high);
|
||||
void dcn316_smu_set_dram_addr_low(struct clk_mgr_internal *clk_mgr, uint32_t addr_low);
|
||||
void dcn316_smu_transfer_dpm_table_smu_2_dram(struct clk_mgr_internal *clk_mgr);
|
||||
void dcn316_smu_transfer_wm_table_dram_2_smu(struct clk_mgr_internal *clk_mgr);
|
||||
void dcn316_smu_request_voltage_via_phyclk(struct clk_mgr_internal *clk_mgr, int requested_phyclk_khz);
|
||||
void dcn316_smu_enable_pme_wa(struct clk_mgr_internal *clk_mgr);
|
||||
void dcn316_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable);
|
||||
|
||||
#endif /* DAL_DC_316_SMU_H_ */
|
||||
|
|
@ -66,6 +66,7 @@
|
|||
#include "dcn302/dcn302_resource.h"
|
||||
#include "dcn303/dcn303_resource.h"
|
||||
#include "dcn31/dcn31_resource.h"
|
||||
#include "dcn316/dcn316_resource.h"
|
||||
#endif
|
||||
|
||||
#define DC_LOGGER_INIT(logger)
|
||||
|
|
@ -250,6 +251,9 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
|
|||
case DCN_VERSION_3_1:
|
||||
res_pool = dcn31_create_resource_pool(init_data, dc);
|
||||
break;
|
||||
case DCN_VERSION_3_16:
|
||||
res_pool = dcn316_create_resource_pool(init_data, dc);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,56 @@
|
|||
#
|
||||
# Copyright 2021 Advanced Micro Devices, Inc.
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a
|
||||
# copy of this software and associated documentation files (the "Software"),
|
||||
# to deal in the Software without restriction, including without limitation
|
||||
# the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
# and/or sell copies of the Software, and to permit persons to whom the
|
||||
# Software is furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
# THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
# OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
# ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
# OTHER DEALINGS IN THE SOFTWARE.
|
||||
#
|
||||
# Authors: AMD
|
||||
#
|
||||
# Makefile for dcn316.
|
||||
|
||||
DCN316 = dcn316_resource.o
|
||||
|
||||
ifdef CONFIG_X86
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn316/dcn316_resource.o := -msse
|
||||
endif
|
||||
|
||||
ifdef CONFIG_PPC64
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn316/dcn316_resource.o := -mhard-float -maltivec
|
||||
endif
|
||||
|
||||
ifdef CONFIG_CC_IS_GCC
|
||||
ifeq ($(call cc-ifversion, -lt, 0701, y), y)
|
||||
IS_OLD_GCC = 1
|
||||
endif
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn316/dcn316_resource.o += -mhard-float
|
||||
endif
|
||||
|
||||
ifdef CONFIG_X86
|
||||
ifdef IS_OLD_GCC
|
||||
# Stack alignment mismatch, proceed with caution.
|
||||
# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3
|
||||
# (8B stack alignment).
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn316/dcn316_resource.o += -mpreferred-stack-boundary=4
|
||||
else
|
||||
CFLAGS_$(AMDDALPATH)/dc/dcn316/dcn316_resource.o += -msse2
|
||||
endif
|
||||
endif
|
||||
|
||||
AMD_DAL_DCN316 = $(addprefix $(AMDDALPATH)/dc/dcn316/,$(DCN316))
|
||||
|
||||
AMD_DISPLAY_FILES += $(AMD_DAL_DCN316)
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,42 @@
|
|||
/*
|
||||
* Copyright 2021 Advanced Micro Devices, Inc.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
|
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
|
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Authors: AMD
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _DCN316_RESOURCE_H_
|
||||
#define _DCN316_RESOURCE_H_
|
||||
|
||||
#include "core_types.h"
|
||||
|
||||
#define TO_DCN316_RES_POOL(pool)\
|
||||
container_of(pool, struct dcn316_resource_pool, base)
|
||||
|
||||
struct dcn316_resource_pool {
|
||||
struct resource_pool base;
|
||||
};
|
||||
|
||||
struct resource_pool *dcn316_create_resource_pool(
|
||||
const struct dc_init_data *init_data,
|
||||
struct dc *dc);
|
||||
|
||||
#endif /* _DCN316_RESOURCE_H_ */
|
||||
Loading…
Reference in New Issue