[TG3]: Add phy workaround
Add some PHY workaround code to reduce jitter on some PHYs. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1030,6 +1030,12 @@ out:
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
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}
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else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
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}
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/* Set Extended packet length bit (bit 14) on all chips that */
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/* support jumbo frames */
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if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
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@ -10360,10 +10366,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
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tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
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if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
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(GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787))
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tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
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tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
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else
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tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
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}
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tp->coalesce_mode = 0;
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if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
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@ -2215,6 +2215,7 @@ struct tg3 {
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#define TG3_FLG2_HW_TSO_2 0x08000000
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#define TG3_FLG2_HW_TSO (TG3_FLG2_HW_TSO_1 | TG3_FLG2_HW_TSO_2)
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#define TG3_FLG2_1SHOT_MSI 0x10000000
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#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
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u32 split_mode_max_reqs;
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#define SPLIT_MODE_5704_MAX_REQ 3
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