Add PWM supprt on Phytium SoCs
This patch adds a driver for the PWM controller found on Phytium SoCs.
source from Phytium commit 1a1d6db9a1e4e60f80e9c5360056ef0c84f446b1.
Reviewed-by: Hongbo Mao <maohongbo@phytium.com.cn>
(cherry picked from commit 14f5c0b48c)
Signed-off-by: Alex Shi <alexsshi@tencent.com>
This commit is contained in:
Malloy Liu
Jianping Liu
parent
7e5367c0bd
commit
c40f60149f
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@ -1,10 +0,0 @@
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--- MAINTAINERS
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+++ MAINTAINERS
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@@ -1856,6 +1856,7 @@ F: Documentation/devicetree/bindings/spi/spi-phytium.txt
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W: https://www.phytium.com.cn
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F: arch/arm64/boot/dts/phytium/*
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F: Documentation/devicetree/bindings/net/can/phytium-can.txt
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+F: drivers/net/can/phytium/*
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ARM/PLEB SUPPORT
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M: Peter Chubb <pleb@gelato.unsw.edu.au>
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@ -345,6 +345,16 @@ config PWM_PCA9685
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To compile this driver as a module, choose M here: the module
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will be called pwm-pca9685.
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config PWM_PHYTIUM
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tristate "Phytium PWM support"
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depends on ARCH_PHYTIUM
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help
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Generic PWM framework driver for the PWM controller found on
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Phytium SoCs.
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To compile this driver as a module, choose M here: the module
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will be called pwm-phytium.
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config PWM_PUV3
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tristate "PKUnity NetBook-0916 PWM support"
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depends on ARCH_PUV3
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@ -33,6 +33,7 @@ obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o
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obj-$(CONFIG_PWM_MXS) += pwm-mxs.o
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obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o
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obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
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obj-$(CONFIG_PWM_PHYTIUM) += pwm-phytium.o
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obj-$(CONFIG_PWM_PUV3) += pwm-puv3.o
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obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
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obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
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@ -0,0 +1,560 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Phytium PWM driver
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*
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* Copyright (C) 2021-2023, Phytium Technology Co., Ltd.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/export.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/time.h>
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#define REG_TCNT 0x00
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#define REG_TCTRL 0x04
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#define REG_STAT 0x08
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#define REG_TPERIOD 0x0c
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#define REG_PWMCTRL 0x10
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#define REG_PWMCCR 0x14
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#define TCTRL_DIV_MASK 0x1ff8
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#define TCTRL_PWMMOD_MASK 0x4
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#define TCTRL_CAPMOD_MASK 0x3
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#define PWM_PERIOD_MASK 0xffff
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#define PWM_DUTY_MASK 0xffff
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#define PWM_MODE_MASK 0x4
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#define PWM_CTRL_INIT 0xc4
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#define PWM_NUM 2
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#define REG_DBCTRL 0x00
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#define REG_DBCLY 0x04
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#define PWM_UPDBCLY_MASK 0x3ff
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#define PWM_DWDBCLY_MASK 0xffc00
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#define PWM_DB_POLARITY_MASK 0xc
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#define PWM_N(x) ((0x400)*(x))
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#define MAX_PARAMETER 2
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struct phytium_pwm_state {
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int rst;
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int cntmod;
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int dutymod;
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unsigned int div;
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int db_rst;
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unsigned int updbcly;
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unsigned int dwdbcly;
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unsigned int dbpolarity;
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};
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struct phytium_pwm_param {
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int cntmod;
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int dutymod;
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unsigned int div;
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unsigned int updbcly;
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unsigned int dwdbcly;
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unsigned int dbpolarity;
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};
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struct phytium_pwm_variant {
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u8 rst_mask;
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u8 div;
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int counter_mode;
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int periodns;
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int duty_ns;
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int pwm_mode;
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u8 duty_mode;
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int updbcly;
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int dwdbcly;
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};
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struct phytium_pwm_channel {
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u32 period_ns;
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u32 duty_ns;
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u32 tin_ns;
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};
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struct phytium_pwm_chip {
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struct pwm_chip chip;
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struct pwm_state state_pm[PWM_NUM];
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struct phytium_pwm_variant variant;
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struct phytium_pwm_state state;
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u8 inverter_mask;
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u8 disabled_mask;
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int db_init;
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void __iomem *base;
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void __iomem *base1;
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struct phytium_pwm_param parameter[MAX_PARAMETER];
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unsigned int num_parameters;
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struct clk *base_clk;
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};
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static inline struct phytium_pwm_chip *to_phytium_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct phytium_pwm_chip, chip);
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}
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static void pwm_phytium_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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devm_kfree(chip->dev, pwm_get_chip_data(pwm));
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pwm_set_chip_data(pwm, NULL);
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}
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static int pwm_phytium_enable(struct pwm_chip *chip, struct pwm_device *pwm, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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reg = readl(our_chip->base + PWM_N(n) + REG_TCTRL);
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reg |= 0x2;
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our_chip->state_pm[n].enabled = 1;
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writel(reg, our_chip->base + PWM_N(n) + REG_TCTRL);
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return 0;
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}
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static void pwm_phytium_disable(struct pwm_chip *chip, struct pwm_device *pwm, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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reg = readl(our_chip->base + PWM_N(n) + REG_TCTRL);
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reg &= 0xfffffffd;
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our_chip->state_pm[n].enabled = 0;
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writel(reg, our_chip->base + PWM_N(n) + REG_TCTRL);
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}
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static void pwm_phytium_dutymod(struct pwm_chip *chip, int dutymod, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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reg = readl(our_chip->base + PWM_N(n) + REG_PWMCTRL);
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if (dutymod == 0)
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reg &= 0xfffffeff;
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else if (dutymod == 1)
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reg |= 0x100;
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writel(reg, our_chip->base + PWM_N(n) + REG_PWMCTRL);
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}
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static void pwm_phytium_set_div(struct pwm_chip *chip, unsigned int div, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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reg = readl(our_chip->base + PWM_N(n) + REG_TCTRL);
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reg &= 0xffff;
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reg |= (div<<16);
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writel(reg, our_chip->base + PWM_N(n) + REG_TCTRL);
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}
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static void pwm_phytium_set_tmode(struct pwm_chip *chip, int tmode, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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reg = readl(our_chip->base + PWM_N(n) + REG_TCTRL);
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if (tmode == 0)
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reg &= 0xfffffffb;
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else if (tmode == 1)
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reg |= 0x4;
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writel(reg, our_chip->base + PWM_N(n) + REG_TCTRL);
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}
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static void pwm_phytium_set_periodns(struct pwm_chip *chip, unsigned int periodns, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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int div = our_chip->state.div;
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u64 cycles;
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cycles = clk_get_rate(our_chip->base_clk);
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cycles *= (periodns / (div + 1));
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do_div(cycles, NSEC_PER_SEC);
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reg = readl(our_chip->base + PWM_N(n) + REG_TPERIOD);
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cycles = (cycles & PWM_PERIOD_MASK) - 0x1;
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our_chip->state_pm[n].period = cycles;
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writel(cycles, our_chip->base + PWM_N(n) + REG_TPERIOD);
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}
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static void pwm_phytium_set_duty(struct pwm_chip *chip, unsigned int duty, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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int div = our_chip->state.div;
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u64 cycles;
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cycles = clk_get_rate(our_chip->base_clk);
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cycles *= (duty / (div + 1));
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do_div(cycles, NSEC_PER_SEC);
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reg = readl(our_chip->base + PWM_N(n) + REG_PWMCCR);
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cycles = (cycles & PWM_DUTY_MASK) - 0x1;
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our_chip->state_pm[n].duty_cycle = cycles;
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writel(cycles, our_chip->base + PWM_N(n) + REG_PWMCCR);
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}
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static int pwm_phytium_set_dbcly(struct pwm_chip *chip, unsigned int updbcly, unsigned int dwdbcly)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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u64 dbcly, cycles, upcycles, dwcycles;
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reg = readl(our_chip->base + REG_TPERIOD);
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cycles = clk_get_rate(our_chip->base_clk);
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dbcly &= 0x0;
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if (updbcly) {
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upcycles = cycles * updbcly;
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do_div(upcycles, NSEC_PER_SEC);
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if (upcycles < reg)
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dbcly |= (upcycles & PWM_UPDBCLY_MASK);
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else
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return -EINVAL;
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}
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if (dwdbcly) {
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dwcycles = cycles * dwdbcly;
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do_div(dwcycles, NSEC_PER_SEC);
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if (dwcycles < reg)
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dbcly |= ((dwcycles << 10) & PWM_DWDBCLY_MASK);
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else
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return -EINVAL;
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}
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writel(dbcly, our_chip->base1 + REG_DBCLY);
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reg = readl(our_chip->base1 + REG_DBCTRL);
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reg |= 0x30;
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writel(reg, our_chip->base1 + REG_DBCTRL);
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return 0;
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}
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static void pwm_phytium_set_dbpolarity(struct pwm_chip *chip, unsigned int db_polarity)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 reg;
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reg = readl(our_chip->base1 + REG_DBCTRL);
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reg &= 0x33;
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reg |= ((db_polarity<<2) & PWM_DB_POLARITY_MASK);
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writel(reg, our_chip->base1 + REG_DBCTRL);
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}
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static int pwm_phytium_init(struct pwm_chip *chip, struct pwm_device *pwm, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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writel(PWM_CTRL_INIT, our_chip->base + PWM_N(n) + REG_PWMCTRL);
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pwm_phytium_dutymod(chip, our_chip->state.dutymod, n);
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pwm_phytium_set_div(chip, our_chip->state.div, n);
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pwm_phytium_set_tmode(chip, our_chip->state.cntmod, n);
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return 0;
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}
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static int pwm_phytium_db_init(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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pwm_phytium_set_dbcly(chip, our_chip->state.updbcly, our_chip->state.dwdbcly);
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pwm_phytium_set_dbpolarity(chip, our_chip->state.dbpolarity);
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return 0;
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}
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static int __pwm_phytium_config(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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pwm_phytium_init(chip, pwm, 0);
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pwm_phytium_init(chip, pwm, 1);
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return 0;
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}
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static int pwm_phytium_set_polarity(struct pwm_chip *chip, enum pwm_polarity polarity, int n)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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u32 value;
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value = readl(our_chip->base + PWM_N(n) + REG_PWMCTRL);
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if (polarity == PWM_POLARITY_INVERSED) {
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value &= 0xffffff0f;
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value |= 0x30;
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} else if (polarity == PWM_POLARITY_NORMAL) {
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value &= 0xffffff0f;
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value |= 0x40;
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}
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our_chip->state_pm[n].polarity = polarity;
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writel(value, our_chip->base + PWM_N(n) + REG_PWMCTRL);
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return 0;
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}
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static int pwm_phytium_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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const struct pwm_state *state)
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{
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struct phytium_pwm_chip *phytium_pwm = to_phytium_pwm_chip(chip);
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struct pwm_state cstate;
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u32 reg;
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int n;
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pwm_get_state(pwm, &cstate);
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n = pwm->hwpwm & BIT(0);
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if ((state->polarity != cstate.polarity) && !state->enabled)
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pwm_phytium_set_polarity(chip, state->polarity, n);
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if (state->enabled && !cstate.enabled)
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pwm_phytium_enable(chip, pwm, n);
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if (!state->enabled && cstate.enabled)
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pwm_phytium_disable(chip, pwm, n);
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if (state->period != cstate.period) {
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pwm_phytium_set_periodns(chip, state->period, n);
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if ((phytium_pwm->db_init == 1) && (n == 0))
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pwm_phytium_db_init(chip, pwm);
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}
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if (state->duty_cycle != cstate.duty_cycle) {
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if (phytium_pwm->state.dutymod == true) {
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reg = readl(phytium_pwm->base + PWM_N(n) + REG_STAT);
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if ((reg & 0x8) != 0x8)
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pwm_phytium_set_duty(chip, state->duty_cycle, n);
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} else {
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pwm_phytium_set_duty(chip, state->duty_cycle, n);
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}
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}
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return 0;
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}
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static int pwm_phytium_request(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct phytium_pwm_chip *our_chip = to_phytium_pwm_chip(chip);
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struct phytium_pwm_channel *our_chan;
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our_chan = devm_kzalloc(chip->dev, sizeof(*our_chan), GFP_KERNEL);
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if (!our_chan)
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return -ENOMEM;
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pwm_set_chip_data(pwm, our_chan);
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__pwm_phytium_config(&our_chip->chip, our_chip->chip.pwms);
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return 0;
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}
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static const struct pwm_ops pwm_phytium_ops = {
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.request = pwm_phytium_request,
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.free = pwm_phytium_free,
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.apply = pwm_phytium_apply,
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.owner = THIS_MODULE,
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};
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static int phytium_pwm_set_parameter(struct phytium_pwm_chip *priv)
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{
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unsigned int i;
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for (i = 0; i < priv->num_parameters; i++) {
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if (priv->parameter[i].updbcly > 0 || priv->parameter[i].dwdbcly > 0) {
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priv->db_init = 1;
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priv->state.db_rst = 1;
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}
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priv->state.cntmod = priv->parameter[i].cntmod;
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priv->state.dutymod = priv->parameter[i].dutymod;
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priv->state.div = priv->parameter[i].div;
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priv->state.updbcly = priv->parameter[i].updbcly;
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priv->state.dwdbcly = priv->parameter[i].dwdbcly;
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priv->state.dbpolarity = priv->parameter[i].dbpolarity;
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}
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priv->state.rst = 1;
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return 0;
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}
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static int pwm_phytium_probe_parameter(struct phytium_pwm_chip *priv,
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struct device_node *np)
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{
|
||||
int nb, ret, array_size;
|
||||
unsigned int i;
|
||||
|
||||
nb = of_property_count_elems_of_size(np, "phytium,db",
|
||||
sizeof(struct phytium_pwm_param));
|
||||
if (nb <= 0 || nb > MAX_PARAMETER)
|
||||
return -EINVAL;
|
||||
|
||||
priv->num_parameters = nb;
|
||||
array_size = nb * sizeof(struct phytium_pwm_param) / sizeof(u32);
|
||||
ret = of_property_read_u32_array(np, "phytium,db",
|
||||
(u32 *)priv->parameter, array_size);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
for (i = 0; i < priv->num_parameters; i++) {
|
||||
if (priv->parameter[i].cntmod > 1 ||
|
||||
priv->parameter[i].dutymod > 1 ||
|
||||
priv->parameter[i].div > 4096 ||
|
||||
priv->parameter[i].dbpolarity > 3)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return phytium_pwm_set_parameter(priv);
|
||||
}
|
||||
static int pwm_phytium_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
struct phytium_pwm_chip *chip;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
|
||||
|
||||
if (chip == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
chip->chip.dev = &pdev->dev;
|
||||
chip->chip.ops = &pwm_phytium_ops;
|
||||
chip->chip.base = -1;
|
||||
chip->chip.npwm = PWM_NUM;
|
||||
chip->inverter_mask = BIT(PWM_NUM) - 1;
|
||||
|
||||
if (pdev->dev.of_node) {
|
||||
chip->chip.of_xlate = of_pwm_xlate_with_flags;
|
||||
chip->chip.of_pwm_n_cells = 3;
|
||||
} else {
|
||||
if (!pdev->dev.platform_data) {
|
||||
dev_err(&pdev->dev, "no platform data specified\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
memcpy(&chip->variant,
|
||||
pdev->dev.platform_data, sizeof(chip->variant));
|
||||
}
|
||||
ret = pwm_phytium_probe_parameter(chip, np);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to set parameter\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
chip->base1 = devm_ioremap_resource(&pdev->dev, res);
|
||||
chip->base = (chip->base1 + 0x400);
|
||||
|
||||
if (IS_ERR(chip->base)) {
|
||||
dev_err(dev, "failed to get base_addr\n");
|
||||
return PTR_ERR(chip->base);
|
||||
}
|
||||
chip->base_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(chip->base_clk)) {
|
||||
dev_err(dev, "failed to get clk\n");
|
||||
return PTR_ERR(chip->base_clk);
|
||||
}
|
||||
|
||||
ret = clk_prepare_enable(chip->base_clk);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to enable clk\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, chip);
|
||||
|
||||
ret = pwmchip_add(&chip->chip);
|
||||
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to register PWM chip\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pwm_phytium_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct phytium_pwm_chip *chip = platform_get_drvdata(pdev);
|
||||
|
||||
pwmchip_remove(&chip->chip);
|
||||
|
||||
clk_disable_unprepare(chip->base_clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM_SLEEP
|
||||
static int pwm_phytium_pm_init(struct phytium_pwm_chip *priv)
|
||||
{
|
||||
int i;
|
||||
|
||||
__pwm_phytium_config(&priv->chip, priv->chip.pwms);
|
||||
for (i = 0; i < priv->chip.npwm; i++) {
|
||||
writel(priv->state_pm[i].period, priv->base + PWM_N(i) + REG_TPERIOD);
|
||||
if ((priv->db_init == 1) && (i == 0))
|
||||
pwm_phytium_db_init(&priv->chip, priv->chip.pwms);
|
||||
writel(priv->state_pm[i].duty_cycle, priv->base + PWM_N(i) + REG_PWMCTRL);
|
||||
pwm_phytium_set_polarity(&priv->chip, priv->state_pm[i].polarity, i);
|
||||
if (priv->state_pm[i].enabled)
|
||||
pwm_phytium_enable(&priv->chip, priv->chip.pwms, i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pwm_phytium_suspend(struct device *dev)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int pwm_phytium_resume(struct device *dev)
|
||||
{
|
||||
struct phytium_pwm_chip *priv = dev_get_drvdata(dev);
|
||||
|
||||
pwm_phytium_pm_init(priv);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static SIMPLE_DEV_PM_OPS(phytium_pwm_dev_pm_ops, pwm_phytium_suspend, pwm_phytium_resume);
|
||||
|
||||
static const struct of_device_id phytium_pwm_matches[] = {
|
||||
{ .compatible = "phytium,pwm" },
|
||||
{},
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, phytium_pwm_matches);
|
||||
|
||||
static struct platform_driver pwm_phytium_driver = {
|
||||
.driver = {
|
||||
.name = "phytium-pwm",
|
||||
.pm = &phytium_pwm_dev_pm_ops,
|
||||
.of_match_table = phytium_pwm_matches,
|
||||
},
|
||||
.probe = pwm_phytium_probe,
|
||||
.remove = pwm_phytium_remove,
|
||||
};
|
||||
module_platform_driver(pwm_phytium_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Phytium SoC PWM driver");
|
||||
MODULE_AUTHOR("Yang Liu <yangliu2021@phytium.com.cn>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
@ -260,7 +260,7 @@ static int pwm_export_child(struct device *parent, struct pwm_device *pwm)
|
|||
export->child.parent = parent;
|
||||
export->child.devt = MKDEV(0, 0);
|
||||
export->child.groups = pwm_groups;
|
||||
dev_set_name(&export->child, "pwm%u", pwm->hwpwm);
|
||||
dev_set_name(&export->child, "pwm%u", pwm->pwm);
|
||||
|
||||
ret = device_register(&export->child);
|
||||
if (ret) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue