From c388eee21ad20929f440d6fae94c995791c5818b Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Wed, 5 Jun 2013 16:37:17 +0300 Subject: [PATCH] clk: tegra: pllp_out2 divider is int only The pllp_out2 should be integer only, the fractional bit should always be 0. Signed-off-by: Peter De Schrijver Tested-by: Stephen Warren Acked-by: Stephen Warren Signed-off-by: Mike Turquette --- drivers/clk/tegra/clk-tegra114.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index 797e58f2f811..2dd9b0094c97 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -1200,8 +1200,8 @@ static void __init tegra114_pll_init(void __iomem *clk_base, /* PLLP_OUT2 */ clk = tegra_clk_register_divider("pll_p_out2_div", "pll_p", clk_base + PLLP_OUTA, 0, TEGRA_DIVIDER_FIXED | - TEGRA_DIVIDER_ROUND_UP, 24, 8, 1, - &pll_div_lock); + TEGRA_DIVIDER_ROUND_UP | TEGRA_DIVIDER_INT, 24, + 8, 1, &pll_div_lock); clk = tegra_clk_register_pll_out("pll_p_out2", "pll_p_out2_div", clk_base + PLLP_OUTA, 17, 16, CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0,