dt-bindings: memory-controllers: ti,gpmc: Convert to yaml
Convert omap-gpmc.txt to ti,gpmc.yaml. Signed-off-by: Roger Quadros <rogerq@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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Roger Quadros
Tony Lindgren
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Device tree bindings for OMAP general purpose memory controllers (GPMC)
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The actual devices are instantiated from the child nodes of a GPMC node.
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Required properties:
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- compatible: Should be set to one of the following:
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ti,omap2420-gpmc (omap2420)
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ti,omap2430-gpmc (omap2430)
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ti,omap3430-gpmc (omap3430 & omap3630)
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ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
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ti,am3352-gpmc (am335x devices)
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- reg: A resource specifier for the register space
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(see the example below)
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- ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
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completed.
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- #address-cells: Must be set to 2 to allow memory address translation
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- #size-cells: Must be set to 1 to allow CS address passing
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- gpmc,num-cs: The maximum number of chip-select lines that controller
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can support.
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- gpmc,num-waitpins: The maximum number of wait pins that controller can
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support.
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- ranges: Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use:
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<cs-number> 0 <physical address of mapping> <size>
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Currently, calculated values derived from the contents
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of the per-CS register GPMC_CONFIG7 (as set up by the
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bootloader) are used for the physical address decoding.
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As this will change in the future, filling correct
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values here is a requirement.
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- interrupt-controller: The GPMC driver implements and interrupt controller for
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the NAND events "fifoevent" and "termcount" plus the
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rising/falling edges on the GPMC_WAIT pins.
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The interrupt number mapping is as follows
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0 - NAND_fifoevent
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1 - NAND_termcount
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2 - GPMC_WAIT0 pin edge
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3 - GPMC_WAIT1 pin edge, and so on.
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- interrupt-cells: Must be set to 2
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- gpio-controller: The GPMC driver implements a GPIO controller for the
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GPMC WAIT pins that can be used as general purpose inputs.
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0 maps to GPMC_WAIT0 pin.
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- gpio-cells: Must be set to 2
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Required properties when using NAND prefetch dma:
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- dmas GPMC NAND prefetch dma channel
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- dma-names Must be set to "rxtx"
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Timing properties for child nodes. All are optional and default to 0.
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- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
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Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
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- gpmc,cs-on-ns: Assertion time
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- gpmc,cs-rd-off-ns: Read deassertion time
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- gpmc,cs-wr-off-ns: Write deassertion time
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ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
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- gpmc,adv-on-ns: Assertion time
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- gpmc,adv-rd-off-ns: Read deassertion time
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- gpmc,adv-wr-off-ns: Write deassertion time
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- gpmc,adv-aad-mux-on-ns: Assertion time for AAD
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- gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD
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- gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD
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WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
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- gpmc,we-on-ns Assertion time
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- gpmc,we-off-ns: Deassertion time
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OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
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- gpmc,oe-on-ns: Assertion time
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- gpmc,oe-off-ns: Deassertion time
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- gpmc,oe-aad-mux-on-ns: Assertion time for AAD
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- gpmc,oe-aad-mux-off-ns: Deassertion time for AAD
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Access time and cycle time timings (in nanoseconds) corresponding to
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GPMC_CONFIG5:
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- gpmc,page-burst-access-ns: Multiple access word delay
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- gpmc,access-ns: Start-cycle to first data valid delay
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- gpmc,rd-cycle-ns: Total read cycle time
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- gpmc,wr-cycle-ns: Total write cycle time
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- gpmc,bus-turnaround-ns: Turn-around time between successive accesses
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- gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
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- gpmc,clk-activation-ns: GPMC clock activation time
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- gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
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data
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Boolean timing parameters. If property is present parameter enabled and
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disabled if omitted:
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- gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
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- gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
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- gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
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accesses to a different CS
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- gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
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accesses to the same CS
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- gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
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- gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
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- gpmc,time-para-granularity: Multiply all access times by 2
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The following are only applicable to OMAP3+ and AM335x:
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- gpmc,wr-access-ns: In synchronous write mode, for single or
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burst accesses, defines the number of
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GPMC_FCLK cycles from start access time
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to the GPMC_CLK rising edge used by the
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memory device for the first data capture.
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- gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
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the time when the first data is driven on
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the address-data bus.
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GPMC chip-select settings properties for child nodes. All are optional.
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- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
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- gpmc,burst-wrap Enables wrap bursting
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- gpmc,burst-read Enables read page/burst mode
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- gpmc,burst-write Enables write page/burst mode
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- gpmc,device-width Total width of device(s) connected to a GPMC
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chip-select in bytes. The GPMC supports 8-bit
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and 16-bit devices and so this property must be
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1 or 2.
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- gpmc,mux-add-data Address and data multiplexing configuration.
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Valid values are 1 for address-address-data
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multiplexing mode and 2 for address-data
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multiplexing mode.
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- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
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is this is not set.
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- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
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is this is not set.
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- gpmc,wait-pin Wait-pin used by client. Must be less than
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"gpmc,num-waitpins".
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- gpmc,wait-on-read Enables wait monitoring on reads.
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- gpmc,wait-on-write Enables wait monitoring on writes.
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Example for an AM33xx board:
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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reg = <0x50000000 0x2000>;
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interrupts = <100>;
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dmas = <&edma 52 0>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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/* child nodes go here */
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};
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@ -0,0 +1,172 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments GPMC Memory Controller device-tree bindings
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maintainers:
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- Tony Lindgren <tony@atomide.com>
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- Roger Quadros <rogerq@kernel.org>
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description:
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The GPMC is a unified memory controller dedicated for interfacing
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with external memory devices like
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- Asynchronous SRAM-like memories and ASICs
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- Asynchronous, synchronous, and page mode burst NOR flash
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- NAND flash
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- Pseudo-SRAM devices
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properties:
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compatible:
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items:
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- enum:
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- ti,am3352-gpmc
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- ti,omap2420-gpmc
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- ti,omap2430-gpmc
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- ti,omap3430-gpmc
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- ti,omap4430-gpmc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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description: |
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Functional clock. Used for bus timing calculations and
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GPMC configuration.
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clock-names:
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items:
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- const: fck
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dmas:
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items:
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- description: DMA channel for GPMC NAND prefetch
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dma-names:
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items:
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- const: rxtx
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"#address-cells": true
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"#size-cells": true
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gpmc,num-cs:
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description: maximum number of supported chip-select lines.
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$ref: /schemas/types.yaml#/definitions/uint32
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gpmc,num-waitpins:
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description: maximum number of supported wait pins.
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$ref: /schemas/types.yaml#/definitions/uint32
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ranges:
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minItems: 1
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description: |
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Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use,
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<cs-number> 0 <physical address of mapping> <size>
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items:
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- description: NAND bank 0
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- description: NOR/SRAM bank 0
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- description: NOR/SRAM bank 1
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'#interrupt-cells':
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const: 2
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interrupt-controller:
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description: |
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The GPMC driver implements and interrupt controller for
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the NAND events "fifoevent" and "termcount" plus the
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rising/falling edges on the GPMC_WAIT pins.
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The interrupt number mapping is as follows
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0 - NAND_fifoevent
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1 - NAND_termcount
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2 - GPMC_WAIT0 pin edge
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3 - GPMC_WAIT1 pin edge, and so on.
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'#gpio-cells':
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const: 2
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gpio-controller:
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description: |
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The GPMC driver implements a GPIO controller for the
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GPMC WAIT pins that can be used as general purpose inputs.
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0 maps to GPMC_WAIT0 pin.
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ti,hwmods:
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description:
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Name of the HWMOD associated with GPMC. This is for legacy
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omap2/3 platforms only.
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$ref: /schemas/types.yaml#/definitions/string
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deprecated: true
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ti,no-idle-on-init:
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description:
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Prevent idling the module at init. This is for legacy omap2/3
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platforms only.
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type: boolean
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deprecated: true
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patternProperties:
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"@[0-7],[a-f0-9]+$":
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type: object
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description: |
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The child device node represents the device connected to the GPMC
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bus. The device can be a NAND chip, SRAM device, NOR device
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or an ASIC.
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allOf:
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- $ref: "ti,gpmc-child.yaml"
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unevaluatedProperties: false
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required:
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- compatible
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- reg
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- gpmc,num-cs
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- gpmc,num-waitpins
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- "#address-cells"
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- "#size-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/gpio/gpio.h>
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gpmc: memory-controller@50000000 {
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compatible = "ti,am3352-gpmc";
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reg = <0x50000000 0x2000>;
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interrupts = <100>;
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clocks = <&l3s_clkctrl>;
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clock-names = "fck";
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dmas = <&edma 52 0>;
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dma-names = "rxtx";
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gpmc,num-cs = <8>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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nand@0,0 {
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compatible = "ti,omap2-nand";
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reg = <0 0 4>;
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interrupt-parent = <&gpmc>;
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interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
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<1 IRQ_TYPE_NONE>; /* termcount */
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ti,nand-xfer-type = "prefetch-dma";
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ti,nand-ecc-opt = "bch16";
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ti,elm-id = <&elm>;
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rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
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};
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};
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