Devicetree changes for TI K3 platforms for v5.12 merge window:
- Common fixups: PMU compatible, MMC dtbs_check warnings squelch - J7200: R5F, PCIe, SERDES support - J721E: PCIE fixups -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE+KKGk1TrgjIXoxo03bWEnRc2JJ0FAmAVV9oACgkQ3bWEnRc2 JJ1jjA/9EHhyfoIrdnCf/1/x/vBKcpIn/9BZ5rDgeBsmWtipglBQkqnwE341kijs Gv15azQGx84LJPlgNG9TbozNHXEX1mLkJkEEX0C/PFh6GuF+Saoeuh8xrOVixwo1 xgkFjrXXHHb4aUOLGzjEKmCeFaWDnmIhJIupTOMa7FJm/GuV3m81kY+R66nW+pWs kb7KWWy/hum/yEHeF1uYRdv4TRg2aTKeJTqlMTdMjl6IJWq/GiZCs7UrVGQPpCAt E/1tRwHQJDCY0VYWrmoBSiCtAa8dikE6wyvz5Qmk/aWTBEjMbBN4DkZJJsSNXi2B qUan+q3atirf+JaPEqpqVdGilOeFcjJE0amkzY8k4a2kxJg2qizbZiW66rSDmo1y 7BZZEzO1UBKzBiZz7HbZj1gfZypn44k5P474ZA5IMrcUJvxZlfhVAuJ2Uz7tCGPO 4mqyS43c0Oidh5rjSUjwUjuz4r7eZ5gFWUuoQVrkTzEz6J2Vx150bb2qXhLJob6M ywN0xfEYMX6LBwkj2sGeKO5tnyeZBsZysXFemmF+HtjLuwSujubPK4h5TbcB64FY CPfshpvRrz7mla74w45RW1nUp+DnAs21ZuC33gLGh45n0Jshl5sJyRPD67yXHdqN D4BP48fZQZ3tFQkaSYnHXoASUcEz8IsWES10vpoznoOpP77wBa4= =mq2V -----END PGP SIGNATURE----- Merge tag 'ti-k3-dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux into arm/dt Devicetree changes for TI K3 platforms for v5.12 merge window: - Common fixups: PMU compatible, MMC dtbs_check warnings squelch - J7200: R5F, PCIe, SERDES support - J721E: PCIE fixups * tag 'ti-k3-dt-for-v5.12' of git://git.kernel.org/pub/scm/linux/kernel/git/nmenon/linux: arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific arm64: dts: ti: k3: mmc: fix dtbs_check warnings arm64: dts: ti: k3-j7200-som-p0: Add DDR carveout memory nodes for R5Fs arm64: dts: ti: k3-j7200-som-p0: Add mailboxes to R5Fs arm64: dts: ti: k3-j7200: Add R5F cluster nodes arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0 arm64: dts: ti: k3-j7200-main: Add PCIe device tree node arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions Link: https://lore.kernel.org/r/20210130131422.yvq2edxfongys7x5@pendant Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
c2f76057d3
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@ -256,7 +256,7 @@
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#size-cells = <0>;
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};
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sdhci0: sdhci@4f80000 {
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sdhci0: mmc@4f80000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
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power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>;
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@ -280,7 +280,7 @@
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dma-coherent;
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};
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sdhci1: sdhci@4fa0000 {
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sdhci1: mmc@4fa0000 {
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compatible = "ti,am654-sdhci-5.1";
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reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>;
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power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
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@ -56,7 +56,7 @@
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};
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pmu: pmu {
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compatible = "arm,armv8-pmuv3";
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compatible = "arm,cortex-a53-pmu";
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/* Recommendation from GIC500 TRM Table A.3 */
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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@ -6,8 +6,10 @@
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/dts-v1/;
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#include "k3-j7200-som-p0.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/mux/ti-serdes.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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chosen {
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@ -218,3 +220,39 @@
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ti,adc-channels = <0 1 2 3 4 5 6 7>;
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};
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};
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&serdes_refclk {
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clock-frequency = <100000000>;
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};
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&serdes0 {
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serdes0_pcie_link: phy@0 {
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reg = <0>;
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cdns,num-lanes = <2>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_PCIE>;
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resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
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};
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serdes0_qsgmii_link: phy@1 {
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reg = <2>;
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cdns,num-lanes = <1>;
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#phy-cells = <0>;
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cdns,phy-type = <PHY_TYPE_QSGMII>;
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resets = <&serdes_wiz0 3>;
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};
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};
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&pcie1_rc {
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reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
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phys = <&serdes0_pcie_link>;
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phy-names = "pcie-phy";
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num-lanes = <2>;
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};
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&pcie1_ep {
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phys = <&serdes0_pcie_link>;
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phy-names = "pcie-phy";
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num-lanes = <2>;
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status = "disabled";
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};
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@ -2,9 +2,16 @@
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/*
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* Device Tree Source for J7200 SoC Family Main Domain peripherals
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*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/ {
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serdes_refclk: serdes-refclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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};
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&cbass_main {
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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@ -499,8 +506,8 @@
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reg = <0x00 0x04f80000 0x00 0x260>, <0x00 0x4f88000 0x00 0x134>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&k3_clks 91 3>, <&k3_clks 91 0>;
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clock-names = "clk_ahb", "clk_xin";
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clocks = <&k3_clks 91 0>, <&k3_clks 91 3>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-mmc-hs = <0x0>;
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ti,otap-del-sel-ddr52 = <0x6>;
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@ -518,8 +525,8 @@
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reg = <0x00 0x04fb0000 0x00 0x260>, <0x00 0x4fb8000 0x00 0x134>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
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clock-names = "clk_xin", "clk_ahb";
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clocks = <&k3_clks 92 2>, <&k3_clks 92 1>;
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clock-names = "clk_ahb", "clk_xin";
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clocks = <&k3_clks 92 1>, <&k3_clks 92 2>;
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ti,otap-del-sel-legacy = <0x0>;
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ti,otap-del-sel-sd-hs = <0x0>;
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ti,otap-del-sel-sdr12 = <0xf>;
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@ -531,6 +538,110 @@
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dma-coherent;
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};
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serdes_wiz0: wiz@5060000 {
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compatible = "ti,j721e-wiz-10g";
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#address-cells = <1>;
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#size-cells = <1>;
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power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 292 11>, <&k3_clks 292 85>, <&serdes_refclk>;
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clock-names = "fck", "core_ref_clk", "ext_ref_clk";
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num-lanes = <4>;
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#reset-cells = <1>;
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ranges = <0x5060000 0x0 0x5060000 0x10000>;
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assigned-clocks = <&k3_clks 292 85>;
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assigned-clock-parents = <&k3_clks 292 89>;
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wiz0_pll0_refclk: pll0-refclk {
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clocks = <&k3_clks 292 85>, <&serdes_refclk>;
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clock-output-names = "wiz0_pll0_refclk";
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#clock-cells = <0>;
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assigned-clocks = <&wiz0_pll0_refclk>;
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assigned-clock-parents = <&k3_clks 292 85>;
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};
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wiz0_pll1_refclk: pll1-refclk {
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clocks = <&k3_clks 292 85>, <&serdes_refclk>;
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clock-output-names = "wiz0_pll1_refclk";
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#clock-cells = <0>;
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assigned-clocks = <&wiz0_pll1_refclk>;
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assigned-clock-parents = <&k3_clks 292 85>;
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};
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wiz0_refclk_dig: refclk-dig {
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clocks = <&k3_clks 292 85>, <&serdes_refclk>;
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clock-output-names = "wiz0_refclk_dig";
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#clock-cells = <0>;
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assigned-clocks = <&wiz0_refclk_dig>;
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assigned-clock-parents = <&k3_clks 292 85>;
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};
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wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
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clocks = <&wiz0_refclk_dig>;
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#clock-cells = <0>;
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};
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serdes0: serdes@5060000 {
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compatible = "ti,j721e-serdes-10g";
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reg = <0x05060000 0x00010000>;
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reg-names = "torrent_phy";
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resets = <&serdes_wiz0 0>;
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reset-names = "torrent_reset";
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clocks = <&wiz0_pll0_refclk>;
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clock-names = "refclk";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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pcie1_rc: pcie@2910000 {
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compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
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reg = <0x00 0x02910000 0x00 0x1000>,
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<0x00 0x02917000 0x00 0x400>,
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<0x00 0x0d800000 0x00 0x00800000>,
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<0x00 0x18000000 0x00 0x00001000>;
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reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
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interrupt-names = "link_state";
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interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
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device_type = "pci";
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ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
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max-link-speed = <3>;
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num-lanes = <4>;
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power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 240 6>;
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clock-names = "fck";
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x0 0xf>;
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cdns,no-bar-match-nbits = <64>;
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vendor-id = /bits/ 16 <0x104c>;
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device-id = /bits/ 16 <0xb00f>;
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msi-map = <0x0 &gic_its 0x0 0x10000>;
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dma-coherent;
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ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
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<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
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dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
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};
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pcie1_ep: pcie-ep@2910000 {
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compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
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reg = <0x00 0x02910000 0x00 0x1000>,
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<0x00 0x02917000 0x00 0x400>,
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<0x00 0x0d800000 0x00 0x00800000>,
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<0x00 0x18000000 0x00 0x08000000>;
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reg-names = "intd_cfg", "user_cfg", "reg", "mem";
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interrupt-names = "link_state";
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interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
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ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
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max-link-speed = <3>;
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num-lanes = <4>;
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power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 240 6>;
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clock-names = "fck";
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max-functions = /bits/ 8 <6>;
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dma-coherent;
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};
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usbss0: cdns-usb@4104000 {
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compatible = "ti,j721e-usb";
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reg = <0x00 0x4104000 0x00 0x100>;
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@ -560,4 +671,44 @@
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dr_mode = "otg";
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};
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};
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main_r5fss0: r5fss@5c00000 {
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compatible = "ti,j7200-r5fss";
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ti,cluster-mode = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
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<0x5d00000 0x00 0x5d00000 0x20000>;
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power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
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main_r5fss0_core0: r5f@5c00000 {
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compatible = "ti,j7200-r5f";
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reg = <0x5c00000 0x00010000>,
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<0x5c10000 0x00010000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <245>;
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ti,sci-proc-ids = <0x06 0xff>;
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resets = <&k3_reset 245 1>;
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firmware-name = "j7200-main-r5f0_0-fw";
|
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ti,atcm-enable = <1>;
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ti,btcm-enable = <1>;
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ti,loczrama = <1>;
|
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};
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main_r5fss0_core1: r5f@5d00000 {
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compatible = "ti,j7200-r5f";
|
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reg = <0x5d00000 0x00008000>,
|
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<0x5d10000 0x00008000>;
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reg-names = "atcm", "btcm";
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ti,sci = <&dmsc>;
|
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ti,sci-dev-id = <246>;
|
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ti,sci-proc-ids = <0x07 0xff>;
|
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resets = <&k3_reset 246 1>;
|
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firmware-name = "j7200-main-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
/*
|
||||
* Device Tree Source for J7200 SoC Family MCU/WAKEUP Domain peripherals
|
||||
*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
&cbass_mcu_wakeup {
|
||||
|
|
@ -289,4 +289,44 @@
|
|||
compatible = "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
|
||||
mcu_r5fss0: r5fss@41000000 {
|
||||
compatible = "ti,j7200-r5fss";
|
||||
ti,cluster-mode = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x41000000 0x00 0x41000000 0x20000>,
|
||||
<0x41400000 0x00 0x41400000 0x20000>;
|
||||
power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
mcu_r5fss0_core0: r5f@41000000 {
|
||||
compatible = "ti,j7200-r5f";
|
||||
reg = <0x41000000 0x00010000>,
|
||||
<0x41010000 0x00010000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <250>;
|
||||
ti,sci-proc-ids = <0x01 0xff>;
|
||||
resets = <&k3_reset 250 1>;
|
||||
firmware-name = "j7200-mcu-r5f0_0-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1: r5f@41400000 {
|
||||
compatible = "ti,j7200-r5f";
|
||||
reg = <0x41400000 0x00008000>,
|
||||
<0x41410000 0x00008000>;
|
||||
reg-names = "atcm", "btcm";
|
||||
ti,sci = <&dmsc>;
|
||||
ti,sci-dev-id = <251>;
|
||||
ti,sci-proc-ids = <0x02 0xff>;
|
||||
resets = <&k3_reset 251 1>;
|
||||
firmware-name = "j7200-mcu-r5f0_1-fw";
|
||||
ti,atcm-enable = <1>;
|
||||
ti,btcm-enable = <1>;
|
||||
ti,loczrama = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
|
@ -25,6 +25,60 @@
|
|||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa0100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa1100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa2100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3000000 0x00 0x100000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
|
||||
compatible = "shared-dma-pool";
|
||||
reg = <0x00 0xa3100000 0x00 0xf00000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
rtos_ipc_memory_region: ipc-memories@a4000000 {
|
||||
reg = <0x00 0xa4000000 0x00 0x00800000>;
|
||||
alignment = <0x1000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -141,6 +195,30 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
|
||||
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
|
||||
<&mcu_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&mcu_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>;
|
||||
memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
|
||||
<&mcu_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core0 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>;
|
||||
memory-region = <&main_r5fss0_core0_dma_memory_region>,
|
||||
<&main_r5fss0_core0_memory_region>;
|
||||
};
|
||||
|
||||
&main_r5fss0_core1 {
|
||||
mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>;
|
||||
memory-region = <&main_r5fss0_core1_dma_memory_region>,
|
||||
<&main_r5fss0_core1_memory_region>;
|
||||
};
|
||||
|
||||
&main_i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&main_i2c0_pins_default>;
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@
|
|||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -28,38 +28,6 @@
|
|||
#size-cells = <1>;
|
||||
ranges = <0x0 0x0 0x00100000 0x1c000>;
|
||||
|
||||
pcie0_ctrl: syscon@4070 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004070 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4070 0x4070 0x4>;
|
||||
};
|
||||
|
||||
pcie1_ctrl: syscon@4074 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004074 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4074 0x4074 0x4>;
|
||||
};
|
||||
|
||||
pcie2_ctrl: syscon@4078 {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x00004078 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x4078 0x4078 0x4>;
|
||||
};
|
||||
|
||||
pcie3_ctrl: syscon@407c {
|
||||
compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
|
||||
reg = <0x0000407c 0x4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x407c 0x407c 0x4>;
|
||||
};
|
||||
|
||||
serdes_ln_ctrl: mux@4080 {
|
||||
compatible = "mmio-mux";
|
||||
reg = <0x00004080 0x50>;
|
||||
|
|
@ -618,7 +586,7 @@
|
|||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -645,13 +613,12 @@
|
|||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 239 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
|
|
@ -667,7 +634,7 @@
|
|||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -694,13 +661,12 @@
|
|||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 240 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
|
|
@ -716,7 +682,7 @@
|
|||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -743,13 +709,12 @@
|
|||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 342 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 241 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
|
|
@ -765,7 +730,7 @@
|
|||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
|
||||
device_type = "pci";
|
||||
ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
|
@ -792,13 +757,12 @@
|
|||
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
|
||||
interrupt-names = "link_state";
|
||||
interrupts = <GIC_SPI 354 IRQ_TYPE_EDGE_RISING>;
|
||||
ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
|
||||
ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
|
||||
max-link-speed = <3>;
|
||||
num-lanes = <2>;
|
||||
power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
|
||||
clocks = <&k3_clks 242 1>;
|
||||
clock-names = "fck";
|
||||
cdns,max-outbound-regions = <16>;
|
||||
max-functions = /bits/ 8 <6>;
|
||||
max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
|
||||
dma-coherent;
|
||||
|
|
@ -1068,13 +1032,13 @@
|
|||
clock-names = "gpio";
|
||||
};
|
||||
|
||||
main_sdhci0: sdhci@4f80000 {
|
||||
main_sdhci0: mmc@4f80000 {
|
||||
compatible = "ti,j721e-sdhci-8bit";
|
||||
reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
|
||||
assigned-clocks = <&k3_clks 91 1>;
|
||||
assigned-clock-parents = <&k3_clks 91 2>;
|
||||
bus-width = <8>;
|
||||
|
|
@ -1090,13 +1054,13 @@
|
|||
dma-coherent;
|
||||
};
|
||||
|
||||
main_sdhci1: sdhci@4fb0000 {
|
||||
main_sdhci1: mmc@4fb0000 {
|
||||
compatible = "ti,j721e-sdhci-4bit";
|
||||
reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
|
||||
assigned-clocks = <&k3_clks 92 0>;
|
||||
assigned-clock-parents = <&k3_clks 92 1>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
|
|
@ -1110,13 +1074,13 @@
|
|||
dma-coherent;
|
||||
};
|
||||
|
||||
main_sdhci2: sdhci@4f98000 {
|
||||
main_sdhci2: mmc@4f98000 {
|
||||
compatible = "ti,j721e-sdhci-4bit";
|
||||
reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
|
||||
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
||||
power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
|
||||
clock-names = "clk_ahb", "clk_xin";
|
||||
clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
|
||||
assigned-clocks = <&k3_clks 93 0>;
|
||||
assigned-clock-parents = <&k3_clks 93 1>;
|
||||
ti,otap-del-sel-legacy = <0x0>;
|
||||
|
|
|
|||
|
|
@ -115,7 +115,7 @@
|
|||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue