ARM: KVM: Move GP registers into the CPU context structure
Continuing our rework of the CPU context, we now move the GP registers into the CPU context structure. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
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@ -68,12 +68,12 @@ static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
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static inline unsigned long *vcpu_pc(struct kvm_vcpu *vcpu)
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{
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return &vcpu->arch.regs.usr_regs.ARM_pc;
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return &vcpu->arch.ctxt.gp_regs.usr_regs.ARM_pc;
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}
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static inline unsigned long *vcpu_cpsr(struct kvm_vcpu *vcpu)
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{
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return &vcpu->arch.regs.usr_regs.ARM_cpsr;
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return &vcpu->arch.ctxt.gp_regs.usr_regs.ARM_cpsr;
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}
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static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
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@ -83,13 +83,13 @@ static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
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static inline bool mode_has_spsr(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
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unsigned long cpsr_mode = vcpu->arch.ctxt.gp_regs.usr_regs.ARM_cpsr & MODE_MASK;
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return (cpsr_mode > USR_MODE && cpsr_mode < SYSTEM_MODE);
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}
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static inline bool vcpu_mode_priv(struct kvm_vcpu *vcpu)
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{
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unsigned long cpsr_mode = vcpu->arch.regs.usr_regs.ARM_cpsr & MODE_MASK;
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unsigned long cpsr_mode = vcpu->arch.ctxt.gp_regs.usr_regs.ARM_cpsr & MODE_MASK;
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return cpsr_mode > USR_MODE;;
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}
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@ -89,6 +89,7 @@ struct kvm_vcpu_fault_info {
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};
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struct kvm_cpu_context {
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struct kvm_regs gp_regs;
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struct vfp_hard_struct vfp;
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u32 cp15[NR_CP15_REGS];
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};
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@ -98,8 +99,6 @@ typedef struct kvm_cpu_context kvm_cpu_context_t;
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struct kvm_vcpu_arch {
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struct kvm_cpu_context ctxt;
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struct kvm_regs regs;
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int target; /* Processor target */
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DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
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@ -176,15 +176,15 @@ int main(void)
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DEFINE(VCPU_HOST_CTXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
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DEFINE(CPU_CTXT_VFP, offsetof(struct kvm_cpu_context, vfp));
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DEFINE(CPU_CTXT_CP15, offsetof(struct kvm_cpu_context, cp15));
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DEFINE(VCPU_REGS, offsetof(struct kvm_vcpu, arch.regs));
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DEFINE(VCPU_USR_REGS, offsetof(struct kvm_vcpu, arch.regs.usr_regs));
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DEFINE(VCPU_SVC_REGS, offsetof(struct kvm_vcpu, arch.regs.svc_regs));
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DEFINE(VCPU_ABT_REGS, offsetof(struct kvm_vcpu, arch.regs.abt_regs));
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DEFINE(VCPU_UND_REGS, offsetof(struct kvm_vcpu, arch.regs.und_regs));
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DEFINE(VCPU_IRQ_REGS, offsetof(struct kvm_vcpu, arch.regs.irq_regs));
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DEFINE(VCPU_FIQ_REGS, offsetof(struct kvm_vcpu, arch.regs.fiq_regs));
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DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
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DEFINE(VCPU_CPSR, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
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DEFINE(CPU_CTXT_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
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DEFINE(GP_REGS_USR, offsetof(struct kvm_regs, usr_regs));
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DEFINE(GP_REGS_SVC, offsetof(struct kvm_regs, svc_regs));
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DEFINE(GP_REGS_ABT, offsetof(struct kvm_regs, abt_regs));
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DEFINE(GP_REGS_UND, offsetof(struct kvm_regs, und_regs));
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DEFINE(GP_REGS_IRQ, offsetof(struct kvm_regs, irq_regs));
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DEFINE(GP_REGS_FIQ, offsetof(struct kvm_regs, fiq_regs));
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DEFINE(GP_REGS_PC, offsetof(struct kvm_regs, usr_regs.ARM_pc));
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DEFINE(GP_REGS_CPSR, offsetof(struct kvm_regs, usr_regs.ARM_cpsr));
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DEFINE(VCPU_HCR, offsetof(struct kvm_vcpu, arch.hcr));
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DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
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DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.fault.hsr));
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@ -112,7 +112,7 @@ static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
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*/
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unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
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{
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unsigned long *reg_array = (unsigned long *)&vcpu->arch.regs;
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unsigned long *reg_array = (unsigned long *)&vcpu->arch.ctxt.gp_regs;
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unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
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switch (mode) {
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@ -147,15 +147,15 @@ unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
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unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
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switch (mode) {
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case SVC_MODE:
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return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_SVC_spsr;
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case ABT_MODE:
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return &vcpu->arch.regs.KVM_ARM_ABT_spsr;
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_ABT_spsr;
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case UND_MODE:
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return &vcpu->arch.regs.KVM_ARM_UND_spsr;
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_UND_spsr;
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case IRQ_MODE:
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return &vcpu->arch.regs.KVM_ARM_IRQ_spsr;
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_IRQ_spsr;
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case FIQ_MODE:
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return &vcpu->arch.regs.KVM_ARM_FIQ_spsr;
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return &vcpu->arch.ctxt.gp_regs.KVM_ARM_FIQ_spsr;
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default:
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BUG();
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}
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@ -55,7 +55,7 @@ static u64 core_reg_offset_from_id(u64 id)
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static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
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{
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u32 __user *uaddr = (u32 __user *)(long)reg->addr;
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struct kvm_regs *regs = &vcpu->arch.regs;
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struct kvm_regs *regs = &vcpu->arch.ctxt.gp_regs;
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u64 off;
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if (KVM_REG_SIZE(reg->id) != 4)
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@ -72,7 +72,7 @@ static int get_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
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static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
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{
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u32 __user *uaddr = (u32 __user *)(long)reg->addr;
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struct kvm_regs *regs = &vcpu->arch.regs;
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struct kvm_regs *regs = &vcpu->arch.ctxt.gp_regs;
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u64 off, val;
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if (KVM_REG_SIZE(reg->id) != 4)
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@ -1,6 +1,17 @@
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#include <linux/irqchip/arm-gic.h>
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#include <asm/assembler.h>
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/* Compat macro, until we get rid of this file entierely */
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#define VCPU_GP_REGS (VCPU_GUEST_CTXT + CPU_CTXT_GP_REGS)
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#define VCPU_USR_REGS (VCPU_GP_REGS + GP_REGS_USR)
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#define VCPU_SVC_REGS (VCPU_GP_REGS + GP_REGS_SVC)
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#define VCPU_ABT_REGS (VCPU_GP_REGS + GP_REGS_ABT)
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#define VCPU_UND_REGS (VCPU_GP_REGS + GP_REGS_UND)
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#define VCPU_IRQ_REGS (VCPU_GP_REGS + GP_REGS_IRQ)
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#define VCPU_FIQ_REGS (VCPU_GP_REGS + GP_REGS_FIQ)
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#define VCPU_PC (VCPU_GP_REGS + GP_REGS_PC)
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#define VCPU_CPSR (VCPU_GP_REGS + GP_REGS_CPSR)
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#define VCPU_USR_REG(_reg_nr) (VCPU_USR_REGS + (_reg_nr * 4))
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#define VCPU_USR_SP (VCPU_USR_REG(13))
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#define VCPU_USR_LR (VCPU_USR_REG(14))
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@ -71,7 +71,7 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
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}
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/* Reset core registers */
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memcpy(&vcpu->arch.regs, reset_regs, sizeof(vcpu->arch.regs));
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memcpy(&vcpu->arch.ctxt.gp_regs, reset_regs, sizeof(vcpu->arch.ctxt.gp_regs));
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/* Reset CP15 registers */
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kvm_reset_coprocs(vcpu);
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