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drm/i915/chv: Add DDL register defines for Cherryview 

Fill in the sprite bits for DDL1/DDL2 registers, and add DDL3.

Still need to write the code to use these...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2014-04-09 13:28:13 +03:00 committed by Daniel Vetter
parent 7d87a7f709
commit c294c545f7
1 changed files with 29 additions and 0 deletions
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29
drivers/gpu/drm/i915/i915_reg.h
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@ -3585,14 +3585,43 @@ enum punit_power_well {
#define DDL_CURSORA_PRECISION_32 (1<<31)
#define DDL_CURSORA_PRECISION_16 (0<<31)
#define DDL_CURSORA_SHIFT 24
#define DDL_SPRITEB_PRECISION_32 (1<<23)
#define DDL_SPRITEB_PRECISION_16 (0<<23)
#define DDL_SPRITEB_SHIFT 16
#define DDL_SPRITEA_PRECISION_32 (1<<15)
#define DDL_SPRITEA_PRECISION_16 (0<<15)
#define DDL_SPRITEA_SHIFT 8
#define DDL_PLANEA_PRECISION_32 (1<<7)
#define DDL_PLANEA_PRECISION_16 (0<<7)
#define DDL_PLANEA_SHIFT 0
#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
#define DDL_CURSORB_PRECISION_32 (1<<31)
#define DDL_CURSORB_PRECISION_16 (0<<31)
#define DDL_CURSORB_SHIFT 24
#define DDL_SPRITED_PRECISION_32 (1<<23)
#define DDL_SPRITED_PRECISION_16 (0<<23)
#define DDL_SPRITED_SHIFT 16
#define DDL_SPRITEC_PRECISION_32 (1<<15)
#define DDL_SPRITEC_PRECISION_16 (0<<15)
#define DDL_SPRITEC_SHIFT 8
#define DDL_PLANEB_PRECISION_32 (1<<7)
#define DDL_PLANEB_PRECISION_16 (0<<7)
#define DDL_PLANEB_SHIFT 0
#define VLV_DDL3 (VLV_DISPLAY_BASE + 0x70058)
#define DDL_CURSORC_PRECISION_32 (1<<31)
#define DDL_CURSORC_PRECISION_16 (0<<31)
#define DDL_CURSORC_SHIFT 24
#define DDL_SPRITEF_PRECISION_32 (1<<23)
#define DDL_SPRITEF_PRECISION_16 (0<<23)
#define DDL_SPRITEF_SHIFT 16
#define DDL_SPRITEE_PRECISION_32 (1<<15)
#define DDL_SPRITEE_PRECISION_16 (0<<15)
#define DDL_SPRITEE_SHIFT 8
#define DDL_PLANEC_PRECISION_32 (1<<7)
#define DDL_PLANEC_PRECISION_16 (0<<7)
#define DDL_PLANEC_SHIFT 0
/* FIFO watermark sizes etc */
#define G4X_FIFO_LINE_SIZE 64