arm64: atomics: move ll/sc atomics into separate header file
In preparation for the Large System Extension (LSE) atomic instructions introduced by ARM v8.1, move the current exclusive load/store (LL/SC) atomics into their own header file. Reviewed-by: Steve Capper <steve.capper@arm.com> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
parent
144e9697a9
commit
c275f76bb4
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@ -30,6 +30,8 @@
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#ifdef __KERNEL__
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#include <asm/atomic_ll_sc.h>
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/*
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* On ARM, ordinary assignment (str instruction) doesn't clear the local
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* strex/ldrex monitor on some implementations. The reason we can use it for
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@ -38,86 +40,6 @@
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#define atomic_read(v) ACCESS_ONCE((v)->counter)
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#define atomic_set(v,i) (((v)->counter) = (i))
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/*
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* AArch64 UP and SMP safe atomic ops. We use load exclusive and
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* store exclusive to ensure that these are atomic. We may loop
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* to ensure that the update happens.
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*/
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#define ATOMIC_OP(op, asm_op) \
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static inline void atomic_##op(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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asm volatile("// atomic_" #op "\n" \
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"1: ldxr %w0, %2\n" \
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" " #asm_op " %w0, %w0, %w3\n" \
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" stxr %w1, %w0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i)); \
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} \
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#define ATOMIC_OP_RETURN(op, asm_op) \
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static inline int atomic_##op##_return(int i, atomic_t *v) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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asm volatile("// atomic_" #op "_return\n" \
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"1: ldxr %w0, %2\n" \
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" " #asm_op " %w0, %w0, %w3\n" \
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" stlxr %w1, %w0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i) \
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: "memory"); \
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\
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smp_mb(); \
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return result; \
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}
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_OP_RETURN(op, asm_op)
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ATOMIC_OPS(add, add)
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ATOMIC_OPS(sub, sub)
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#define atomic_andnot atomic_andnot
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ATOMIC_OP(and, and)
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ATOMIC_OP(andnot, bic)
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ATOMIC_OP(or, orr)
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ATOMIC_OP(xor, eor)
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
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{
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unsigned long tmp;
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int oldval;
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smp_mb();
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asm volatile("// atomic_cmpxchg\n"
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"1: ldxr %w1, %2\n"
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" cmp %w1, %w3\n"
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" b.ne 2f\n"
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" stxr %w0, %w4, %2\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
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: "Ir" (old), "r" (new)
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: "cc");
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smp_mb();
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return oldval;
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}
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#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
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static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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@ -141,6 +63,8 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
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#define atomic_andnot atomic_andnot
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/*
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* 64-bit atomic operations.
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*/
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@ -149,102 +73,8 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
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#define atomic64_read(v) ACCESS_ONCE((v)->counter)
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#define atomic64_set(v,i) (((v)->counter) = (i))
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#define ATOMIC64_OP(op, asm_op) \
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static inline void atomic64_##op(long i, atomic64_t *v) \
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{ \
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long result; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_" #op "\n" \
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"1: ldxr %0, %2\n" \
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" " #asm_op " %0, %0, %3\n" \
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" stxr %w1, %0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i)); \
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} \
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#define ATOMIC64_OP_RETURN(op, asm_op) \
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static inline long atomic64_##op##_return(long i, atomic64_t *v) \
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{ \
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long result; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_" #op "_return\n" \
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"1: ldxr %0, %2\n" \
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" " #asm_op " %0, %0, %3\n" \
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" stlxr %w1, %0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i) \
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: "memory"); \
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\
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smp_mb(); \
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return result; \
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}
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#define ATOMIC64_OPS(op, asm_op) \
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ATOMIC64_OP(op, asm_op) \
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ATOMIC64_OP_RETURN(op, asm_op)
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ATOMIC64_OPS(add, add)
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ATOMIC64_OPS(sub, sub)
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#define atomic64_andnot atomic64_andnot
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ATOMIC64_OP(and, and)
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ATOMIC64_OP(andnot, bic)
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ATOMIC64_OP(or, orr)
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ATOMIC64_OP(xor, eor)
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#undef ATOMIC64_OPS
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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static inline long atomic64_cmpxchg(atomic64_t *ptr, long old, long new)
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{
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long oldval;
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unsigned long res;
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smp_mb();
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asm volatile("// atomic64_cmpxchg\n"
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"1: ldxr %1, %2\n"
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" cmp %1, %3\n"
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" b.ne 2f\n"
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" stxr %w0, %4, %2\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
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: "Ir" (old), "r" (new)
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: "cc");
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smp_mb();
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return oldval;
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}
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#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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static inline long atomic64_dec_if_positive(atomic64_t *v)
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{
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long result;
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unsigned long tmp;
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asm volatile("// atomic64_dec_if_positive\n"
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"1: ldxr %0, %2\n"
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" subs %0, %0, #1\n"
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" b.mi 2f\n"
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" stlxr %w1, %0, %2\n"
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" cbnz %w1, 1b\n"
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" dmb ish\n"
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"2:"
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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:
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: "cc", "memory");
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return result;
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}
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static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
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{
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long c, old;
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@ -266,5 +96,7 @@ static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
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#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
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#define atomic64_andnot atomic64_andnot
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#endif
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#endif
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@ -0,0 +1,215 @@
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/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ATOMIC_LL_SC_H
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#define __ASM_ATOMIC_LL_SC_H
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/*
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* AArch64 UP and SMP safe atomic ops. We use load exclusive and
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* store exclusive to ensure that these are atomic. We may loop
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* to ensure that the update happens.
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*
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* NOTE: these functions do *not* follow the PCS and must explicitly
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* save any clobbered registers other than x0 (regardless of return
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* value). This is achieved through -fcall-saved-* compiler flags for
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* this file, which unfortunately don't work on a per-function basis
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* (the optimize attribute silently ignores these options).
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*/
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#ifndef __LL_SC_INLINE
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#define __LL_SC_INLINE static inline
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#endif
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#ifndef __LL_SC_PREFIX
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#define __LL_SC_PREFIX(x) x
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#endif
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#define ATOMIC_OP(op, asm_op) \
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__LL_SC_INLINE void \
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__LL_SC_PREFIX(atomic_##op(int i, atomic_t *v)) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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asm volatile("// atomic_" #op "\n" \
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"1: ldxr %w0, %2\n" \
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" " #asm_op " %w0, %w0, %w3\n" \
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" stxr %w1, %w0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i)); \
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} \
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#define ATOMIC_OP_RETURN(op, asm_op) \
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__LL_SC_INLINE int \
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__LL_SC_PREFIX(atomic_##op##_return(int i, atomic_t *v)) \
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{ \
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unsigned long tmp; \
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int result; \
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\
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asm volatile("// atomic_" #op "_return\n" \
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"1: ldxr %w0, %2\n" \
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" " #asm_op " %w0, %w0, %w3\n" \
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" stlxr %w1, %w0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i) \
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: "memory"); \
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\
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smp_mb(); \
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return result; \
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}
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#define ATOMIC_OPS(op, asm_op) \
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ATOMIC_OP(op, asm_op) \
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ATOMIC_OP_RETURN(op, asm_op)
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ATOMIC_OPS(add, add)
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ATOMIC_OPS(sub, sub)
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ATOMIC_OP(and, and)
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ATOMIC_OP(andnot, bic)
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ATOMIC_OP(or, orr)
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ATOMIC_OP(xor, eor)
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#undef ATOMIC_OPS
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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__LL_SC_INLINE int
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__LL_SC_PREFIX(atomic_cmpxchg(atomic_t *ptr, int old, int new))
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{
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unsigned long tmp;
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int oldval;
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smp_mb();
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asm volatile("// atomic_cmpxchg\n"
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"1: ldxr %w1, %2\n"
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" cmp %w1, %w3\n"
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" b.ne 2f\n"
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" stxr %w0, %w4, %2\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
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: "Ir" (old), "r" (new)
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: "cc");
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smp_mb();
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return oldval;
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}
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#define ATOMIC64_OP(op, asm_op) \
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__LL_SC_INLINE void \
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__LL_SC_PREFIX(atomic64_##op(long i, atomic64_t *v)) \
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{ \
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long result; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_" #op "\n" \
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"1: ldxr %0, %2\n" \
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" " #asm_op " %0, %0, %3\n" \
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" stxr %w1, %0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i)); \
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} \
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#define ATOMIC64_OP_RETURN(op, asm_op) \
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__LL_SC_INLINE long \
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__LL_SC_PREFIX(atomic64_##op##_return(long i, atomic64_t *v)) \
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{ \
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long result; \
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unsigned long tmp; \
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\
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asm volatile("// atomic64_" #op "_return\n" \
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"1: ldxr %0, %2\n" \
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" " #asm_op " %0, %0, %3\n" \
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" stlxr %w1, %0, %2\n" \
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" cbnz %w1, 1b" \
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
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: "Ir" (i) \
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: "memory"); \
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\
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smp_mb(); \
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return result; \
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}
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#define ATOMIC64_OPS(op, asm_op) \
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ATOMIC64_OP(op, asm_op) \
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ATOMIC64_OP_RETURN(op, asm_op)
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ATOMIC64_OPS(add, add)
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ATOMIC64_OPS(sub, sub)
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ATOMIC64_OP(and, and)
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ATOMIC64_OP(andnot, bic)
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ATOMIC64_OP(or, orr)
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ATOMIC64_OP(xor, eor)
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#undef ATOMIC64_OPS
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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__LL_SC_INLINE long
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__LL_SC_PREFIX(atomic64_cmpxchg(atomic64_t *ptr, long old, long new))
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{
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long oldval;
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unsigned long res;
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smp_mb();
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asm volatile("// atomic64_cmpxchg\n"
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"1: ldxr %1, %2\n"
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" cmp %1, %3\n"
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" b.ne 2f\n"
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" stxr %w0, %4, %2\n"
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" cbnz %w0, 1b\n"
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"2:"
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: "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
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: "Ir" (old), "r" (new)
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: "cc");
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smp_mb();
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return oldval;
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}
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__LL_SC_INLINE long
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__LL_SC_PREFIX(atomic64_dec_if_positive(atomic64_t *v))
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{
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long result;
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unsigned long tmp;
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asm volatile("// atomic64_dec_if_positive\n"
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"1: ldxr %0, %2\n"
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" subs %0, %0, #1\n"
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" b.mi 2f\n"
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" stlxr %w1, %0, %2\n"
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" cbnz %w1, 1b\n"
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" dmb ish\n"
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"2:"
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: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
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:
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: "cc", "memory");
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return result;
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}
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#endif /* __ASM_ATOMIC_LL_SC_H */
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