mtd: brcmnand: add extra SoC support to library
There are a few small hooks required for chips like BCM63138 and the iProc family. Let's introduce those now. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com>
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@ -119,6 +119,9 @@ struct brcmnand_controller {
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unsigned int dma_irq;
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int nand_version;
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/* Some SoCs provide custom interrupt status register(s) */
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struct brcmnand_soc *soc;
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int cmd_pending;
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bool dma_pending;
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struct completion done;
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@ -965,6 +968,17 @@ static irqreturn_t brcmnand_ctlrdy_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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/* Handle SoC-specific interrupt hardware */
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static irqreturn_t brcmnand_irq(int irq, void *data)
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{
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struct brcmnand_controller *ctrl = data;
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if (ctrl->soc->ctlrdy_ack(ctrl->soc))
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return brcmnand_ctlrdy_irq(irq, data);
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return IRQ_NONE;
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}
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static irqreturn_t brcmnand_dma_irq(int irq, void *data)
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{
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struct brcmnand_controller *ctrl = data;
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@ -1153,12 +1167,18 @@ static void brcmnand_cmdfunc(struct mtd_info *mtd, unsigned command,
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if (native_cmd == CMD_PARAMETER_READ ||
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native_cmd == CMD_PARAMETER_CHANGE_COL) {
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int i;
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brcmnand_soc_data_bus_prepare(ctrl->soc);
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/*
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* Must cache the FLASH_CACHE now, since changes in
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* SECTOR_SIZE_1K may invalidate it
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*/
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for (i = 0; i < FC_WORDS; i++)
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ctrl->flash_cache[i] = brcmnand_read_fc(ctrl, i);
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brcmnand_soc_data_bus_unprepare(ctrl->soc);
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/* Cleanup from HW quirk: restore SECTOR_SIZE_1K */
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if (host->hwcfg.sector_size_1k)
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brcmnand_set_sector_size_1k(host,
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@ -1371,10 +1391,15 @@ static int brcmnand_read_by_pio(struct mtd_info *mtd, struct nand_chip *chip,
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brcmnand_send_cmd(host, CMD_PAGE_READ);
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brcmnand_waitfunc(mtd, chip);
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if (likely(buf))
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if (likely(buf)) {
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brcmnand_soc_data_bus_prepare(ctrl->soc);
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for (j = 0; j < FC_WORDS; j++, buf++)
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*buf = brcmnand_read_fc(ctrl, j);
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brcmnand_soc_data_bus_unprepare(ctrl->soc);
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}
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if (oob)
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oob += read_oob_from_regs(ctrl, i, oob,
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mtd->oobsize / trans,
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@ -1546,12 +1571,17 @@ static int brcmnand_write(struct mtd_info *mtd, struct nand_chip *chip,
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lower_32_bits(addr));
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(void)brcmnand_read_reg(ctrl, BRCMNAND_CMD_ADDRESS);
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if (buf)
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if (buf) {
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brcmnand_soc_data_bus_prepare(ctrl->soc);
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for (j = 0; j < FC_WORDS; j++, buf++)
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brcmnand_write_fc(ctrl, j, *buf);
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else if (oob)
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brcmnand_soc_data_bus_unprepare(ctrl->soc);
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} else if (oob) {
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for (j = 0; j < FC_WORDS; j++)
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brcmnand_write_fc(ctrl, j, 0xffffffff);
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}
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if (oob) {
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oob += write_oob_to_regs(ctrl, i, oob,
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@ -1995,6 +2025,11 @@ static int brcmnand_resume(struct device *dev)
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brcmnand_write_reg(ctrl, BRCMNAND_CS_XOR, ctrl->nand_cs_nand_xor);
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brcmnand_write_reg(ctrl, BRCMNAND_CORR_THRESHOLD,
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ctrl->corr_stat_threshold);
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if (ctrl->soc) {
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/* Clear/re-enable interrupt */
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ctrl->soc->ctlrdy_ack(ctrl->soc);
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ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
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}
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list_for_each_entry(host, &ctrl->host_list, node) {
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struct mtd_info *mtd = &host->mtd;
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@ -2139,8 +2174,24 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
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return -ENODEV;
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}
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ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
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DRV_NAME, ctrl);
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/*
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* Some SoCs integrate this controller (e.g., its interrupt bits) in
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* interesting ways
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*/
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if (soc) {
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ctrl->soc = soc;
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ret = devm_request_irq(dev, ctrl->irq, brcmnand_irq, 0,
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DRV_NAME, ctrl);
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/* Enable interrupt */
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ctrl->soc->ctlrdy_ack(ctrl->soc);
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ctrl->soc->ctlrdy_set_enabled(ctrl->soc, true);
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} else {
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/* Use standard interrupt infrastructure */
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ret = devm_request_irq(dev, ctrl->irq, brcmnand_ctlrdy_irq, 0,
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DRV_NAME, ctrl);
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}
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if (ret < 0) {
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dev_err(dev, "can't allocate IRQ %d: error %d\n",
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ctrl->irq, ret);
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@ -23,8 +23,23 @@ struct dev_pm_ops;
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struct brcmnand_soc {
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struct platform_device *pdev;
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void *priv;
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bool (*ctlrdy_ack)(struct brcmnand_soc *soc);
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void (*ctlrdy_set_enabled)(struct brcmnand_soc *soc, bool en);
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void (*prepare_data_bus)(struct brcmnand_soc *soc, bool prepare);
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};
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static inline void brcmnand_soc_data_bus_prepare(struct brcmnand_soc *soc)
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{
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if (soc && soc->prepare_data_bus)
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soc->prepare_data_bus(soc, true);
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}
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static inline void brcmnand_soc_data_bus_unprepare(struct brcmnand_soc *soc)
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{
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if (soc && soc->prepare_data_bus)
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soc->prepare_data_bus(soc, false);
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}
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static inline u32 brcmnand_readl(void __iomem *addr)
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{
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/*
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