NXP/FSL SoC driver fixes for v5.17
- Add missing SoC compatible in existing binding
- Replace kernel.h with the necessary inclusions
- MAINTAINERS file fixes
- Fix memory allocation failure check in guts driver
- Various cleanups and minor fixes
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Merge tag 'soc-fsl-fix-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/fixes
NXP/FSL SoC driver fixes for v5.17
- Add missing SoC compatible in existing binding
- Replace kernel.h with the necessary inclusions
- MAINTAINERS file fixes
- Fix memory allocation failure check in guts driver
- Various cleanups and minor fixes
* tag 'soc-fsl-fix-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux:
soc: fsl: qe: Check of ioremap return value
soc: fsl: qe: fix typo in a comment
soc: fsl: guts: Add a missing memory allocation failure check
soc: fsl: guts: Revert commit 3c0d64e867
soc: fsl: Correct MAINTAINERS database (SOC)
soc: fsl: Correct MAINTAINERS database (QUICC ENGINE LIBRARY)
soc: fsl: Replace kernel.h with the necessary inclusions
dt-bindings: fsl,layerscape-dcfg: add missing compatible for lx2160a
dt-bindings: qoriq-clock: add missing compatible for lx2160a
Link: https://lore.kernel.org/r/20220219012208.21835-1-leoyang.li@nxp.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
c253bf70c6
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@ -8,7 +8,7 @@ Required properties:
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- compatible: Should contain a chip-specific compatible string,
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Chip-specific strings are of the form "fsl,<chip>-dcfg",
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The following <chip>s are known to be supported:
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ls1012a, ls1021a, ls1043a, ls1046a, ls2080a.
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ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a
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- reg : should contain base address and length of DCFG memory-mapped registers
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@ -44,6 +44,7 @@ Required properties:
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* "fsl,ls1046a-clockgen"
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* "fsl,ls1088a-clockgen"
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* "fsl,ls2080a-clockgen"
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* "fsl,lx2160a-clockgen"
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Chassis-version clock strings include:
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* "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks
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* "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks
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@ -7750,8 +7750,7 @@ M: Qiang Zhao <qiang.zhao@nxp.com>
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L: linuxppc-dev@lists.ozlabs.org
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S: Maintained
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F: drivers/soc/fsl/qe/
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F: include/soc/fsl/*qe*.h
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F: include/soc/fsl/*ucc*.h
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F: include/soc/fsl/qe/
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FREESCALE QUICC ENGINE UCC ETHERNET DRIVER
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M: Li Yang <leoyang.li@nxp.com>
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@ -7782,6 +7781,7 @@ F: Documentation/devicetree/bindings/misc/fsl,dpaa2-console.yaml
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F: Documentation/devicetree/bindings/soc/fsl/
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F: drivers/soc/fsl/
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F: include/linux/fsl/
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F: include/soc/fsl/
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FREESCALE SOC FS_ENET DRIVER
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M: Pantelis Antoniou <pantelis.antoniou@gmail.com>
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@ -28,7 +28,6 @@ struct fsl_soc_die_attr {
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static struct guts *guts;
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static struct soc_device_attribute soc_dev_attr;
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static struct soc_device *soc_dev;
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static struct device_node *root;
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/* SoC die attribute definition for QorIQ platform */
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@ -138,7 +137,7 @@ static u32 fsl_guts_get_svr(void)
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static int fsl_guts_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct device_node *root, *np = pdev->dev.of_node;
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struct device *dev = &pdev->dev;
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const struct fsl_soc_die_attr *soc_die;
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const char *machine;
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@ -159,8 +158,14 @@ static int fsl_guts_probe(struct platform_device *pdev)
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root = of_find_node_by_path("/");
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if (of_property_read_string(root, "model", &machine))
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of_property_read_string_index(root, "compatible", 0, &machine);
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if (machine)
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soc_dev_attr.machine = machine;
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if (machine) {
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soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
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if (!soc_dev_attr.machine) {
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of_node_put(root);
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return -ENOMEM;
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}
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}
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of_node_put(root);
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svr = fsl_guts_get_svr();
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soc_die = fsl_soc_die_match(svr, fsl_soc_die);
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@ -195,7 +200,6 @@ static int fsl_guts_probe(struct platform_device *pdev)
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static int fsl_guts_remove(struct platform_device *dev)
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{
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soc_device_unregister(soc_dev);
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of_node_put(root);
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return 0;
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}
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@ -147,7 +147,7 @@ EXPORT_SYMBOL(qe_issue_cmd);
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* memory mapped space.
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* The BRG clock is the QE clock divided by 2.
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* It was set up long ago during the initial boot phase and is
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* is given to us.
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* given to us.
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* Baud rate clocks are zero-based in the driver code (as that maps
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* to port numbers). Documentation uses 1-based numbering.
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*/
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for (i = 0; i < be32_to_cpu(ucode->count); i++)
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iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
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/* Set I-RAM Ready Register */
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iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
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}
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@ -35,6 +35,8 @@ int par_io_init(struct device_node *np)
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if (ret)
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return ret;
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par_io = ioremap(res.start, resource_size(&res));
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if (!par_io)
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return -ENOMEM;
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if (!of_property_read_u32(np, "num-ports", &num_ports))
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num_par_io_ports = num_ports;
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@ -7,7 +7,8 @@
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#ifndef __FSL_DPAA2_FD_H
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#define __FSL_DPAA2_FD_H
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#include <linux/kernel.h>
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#include <linux/byteorder/generic.h>
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#include <linux/types.h>
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/**
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* DOC: DPAA2 FD - Frame Descriptor APIs for DPAA2
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#define _ASM_POWERPC_IMMAP_QE_H
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#ifdef __KERNEL__
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */
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#ifndef _QE_TDM_H_
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#define _QE_TDM_H_
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/types.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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#include <soc/fsl/qe/ucc.h>
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#include <soc/fsl/qe/ucc_fast.h>
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struct device_node;
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/* SI RAM entries */
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#define SIR_LAST 0x0001
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#define SIR_BYTE 0x0002
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#ifndef __UCC_FAST_H__
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#define __UCC_FAST_H__
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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#ifndef __UCC_SLOW_H__
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#define __UCC_SLOW_H__
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <soc/fsl/qe/immap_qe.h>
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#include <soc/fsl/qe/qe.h>
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