powerpc: drop HPC-NET/MPC8641D evaluation platform support
There is no denying that this was an interesting platform in its day. Access to a SMP powerpc platform became a bit more obtainable for folks in the BSP industry in the 2007 era, thanks to this platform. Add to that the move to the black Antec case vs. the generic white 2005 era case of the MPC8548CDS or the retro 1950s 1/2 height horizontal case of the HPC II, and it was pretty interesting to people like myself then. However, like all the other evaluation platforms, the overall system was complex out of necessity, as it tried to showcase all possible features and use-cases. That included an AMP option, where you could run two bootloaders and two kernels over two serial consoles. Peripheral sharing got a bit more tricky when you got to the hard disk and similar. In any case we still have the same circumstance. A relatively rare and expensive evaluation platform that is now 15+ years old and not out there in large numbers in the general public. Removal in 2023 just makes sense. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://msgid.link/20230225201318.3682-3-paul.gortmaker@windriver.com
This commit is contained in:
Paul Gortmaker
Michael Ellerman
parent
f03425a5fd
commit
c1d85f3f75
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@ -1,394 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC8641 HPCN Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*/
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/include/ "mpc8641si-pre.dtsi"
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/ {
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model = "MPC8641HPCN";
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compatible = "fsl,mpc8641hpcn";
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; // 1G at 0x0
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};
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lbc: localbus@ffe05000 {
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reg = <0xffe05000 0x1000>;
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ranges = <0 0 0xef800000 0x00800000
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2 0 0xffdf8000 0x00008000
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3 0 0xffdf0000 0x00008000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x00800000>;
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bank-width = <2>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x00300000>;
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};
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partition@300000 {
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label = "firmware b";
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reg = <0x00300000 0x00100000>;
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read-only;
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};
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partition@400000 {
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label = "fs";
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reg = <0x00400000 0x00300000>;
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};
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partition@700000 {
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label = "firmware a";
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reg = <0x00700000 0x00100000>;
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read-only;
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};
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};
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};
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soc: soc8641@ffe00000 {
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ranges = <0x00000000 0xffe00000 0x00100000>;
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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mdio@24520 {
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phy0: ethernet-phy@0 {
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interrupts = <10 1 0 0>;
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <10 1 0 0>;
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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interrupts = <10 1 0 0>;
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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interrupts = <10 1 0 0>;
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reg = <3>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet2: ethernet@26000 {
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tbi-handle = <&tbi2>;
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phy-handle = <&phy2>;
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phy-connection-type = "rgmii-id";
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};
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mdio@26520 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet3: ethernet@27000 {
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tbi-handle = <&tbi3>;
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phy-handle = <&phy3>;
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phy-connection-type = "rgmii-id";
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};
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mdio@27520 {
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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rmu: rmu@d3000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,srio-rmu";
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reg = <0xd3000 0x500>;
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ranges = <0x0 0xd3000 0x500>;
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message-unit@0 {
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compatible = "fsl,srio-msg-unit";
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reg = <0x0 0x100>;
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interrupts = <
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53 2 0 0 /* msg1_tx_irq */
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54 2 0 0>;/* msg1_rx_irq */
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};
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message-unit@100 {
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compatible = "fsl,srio-msg-unit";
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reg = <0x100 0x100>;
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interrupts = <
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55 2 0 0 /* msg2_tx_irq */
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56 2 0 0>;/* msg2_rx_irq */
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};
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doorbell-unit@400 {
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compatible = "fsl,srio-dbell-unit";
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reg = <0x400 0x80>;
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interrupts = <
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49 2 0 0 /* bell_outb_irq */
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50 2 0 0>;/* bell_inb_irq */
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};
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port-write-unit@4e0 {
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compatible = "fsl,srio-port-write-unit";
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reg = <0x4e0 0x20>;
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interrupts = <48 2 0 0>;
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};
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};
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};
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pci0: pcie@ffe08000 {
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reg = <0xffe08000 0x1000>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
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interrupt-map-mask = <0xff00 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 func 0 - PCI slot 1 */
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0x8800 0 0 1 &mpic 2 1 0 0
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0x8800 0 0 2 &mpic 3 1 0 0
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0x8800 0 0 3 &mpic 4 1 0 0
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0x8800 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 1 - PCI slot 1 */
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0x8900 0 0 1 &mpic 2 1 0 0
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0x8900 0 0 2 &mpic 3 1 0 0
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0x8900 0 0 3 &mpic 4 1 0 0
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0x8900 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 2 - PCI slot 1 */
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0x8a00 0 0 1 &mpic 2 1 0 0
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0x8a00 0 0 2 &mpic 3 1 0 0
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0x8a00 0 0 3 &mpic 4 1 0 0
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0x8a00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 3 - PCI slot 1 */
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0x8b00 0 0 1 &mpic 2 1 0 0
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0x8b00 0 0 2 &mpic 3 1 0 0
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0x8b00 0 0 3 &mpic 4 1 0 0
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0x8b00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 4 - PCI slot 1 */
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0x8c00 0 0 1 &mpic 2 1 0 0
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0x8c00 0 0 2 &mpic 3 1 0 0
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0x8c00 0 0 3 &mpic 4 1 0 0
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0x8c00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 5 - PCI slot 1 */
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0x8d00 0 0 1 &mpic 2 1 0 0
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0x8d00 0 0 2 &mpic 3 1 0 0
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0x8d00 0 0 3 &mpic 4 1 0 0
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0x8d00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 6 - PCI slot 1 */
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0x8e00 0 0 1 &mpic 2 1 0 0
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0x8e00 0 0 2 &mpic 3 1 0 0
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0x8e00 0 0 3 &mpic 4 1 0 0
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0x8e00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 7 - PCI slot 1 */
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0x8f00 0 0 1 &mpic 2 1 0 0
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0x8f00 0 0 2 &mpic 3 1 0 0
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0x8f00 0 0 3 &mpic 4 1 0 0
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0x8f00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x12 func 0 - PCI slot 2 */
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0x9000 0 0 1 &mpic 3 1 0 0
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0x9000 0 0 2 &mpic 4 1 0 0
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0x9000 0 0 3 &mpic 1 1 0 0
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0x9000 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 1 - PCI slot 2 */
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0x9100 0 0 1 &mpic 3 1 0 0
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0x9100 0 0 2 &mpic 4 1 0 0
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0x9100 0 0 3 &mpic 1 1 0 0
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0x9100 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 2 - PCI slot 2 */
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0x9200 0 0 1 &mpic 3 1 0 0
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0x9200 0 0 2 &mpic 4 1 0 0
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0x9200 0 0 3 &mpic 1 1 0 0
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0x9200 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 3 - PCI slot 2 */
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0x9300 0 0 1 &mpic 3 1 0 0
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0x9300 0 0 2 &mpic 4 1 0 0
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0x9300 0 0 3 &mpic 1 1 0 0
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0x9300 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 4 - PCI slot 2 */
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0x9400 0 0 1 &mpic 3 1 0 0
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0x9400 0 0 2 &mpic 4 1 0 0
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0x9400 0 0 3 &mpic 1 1 0 0
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0x9400 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 5 - PCI slot 2 */
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0x9500 0 0 1 &mpic 3 1 0 0
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0x9500 0 0 2 &mpic 4 1 0 0
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0x9500 0 0 3 &mpic 1 1 0 0
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0x9500 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 6 - PCI slot 2 */
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0x9600 0 0 1 &mpic 3 1 0 0
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0x9600 0 0 2 &mpic 4 1 0 0
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0x9600 0 0 3 &mpic 1 1 0 0
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0x9600 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 7 - PCI slot 2 */
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0x9700 0 0 1 &mpic 3 1 0 0
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0x9700 0 0 2 &mpic 4 1 0 0
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0x9700 0 0 3 &mpic 1 1 0 0
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0x9700 0 0 4 &mpic 2 1 0 0
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// IDSEL 0x1c USB
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0xe000 0 0 1 &i8259 12 2
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0xe100 0 0 2 &i8259 9 2
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0xe200 0 0 3 &i8259 10 2
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0xe300 0 0 4 &i8259 11 2
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// IDSEL 0x1d Audio
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0xe800 0 0 1 &i8259 6 2
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// IDSEL 0x1e Legacy
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0xf000 0 0 1 &i8259 7 2
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0xf100 0 0 1 &i8259 7 2
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// IDSEL 0x1f IDE/SATA
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0xf800 0 0 1 &i8259 14 2
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0xf900 0 0 1 &i8259 5 2
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>;
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pcie@0 {
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ranges = <0x02000000 0x0 0x80000000
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0x02000000 0x0 0x80000000
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0x0 0x20000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00010000>;
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uli1575@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <0x02000000 0x0 0x80000000
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0x02000000 0x0 0x80000000
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0x0 0x20000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00010000>;
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isa@1e {
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device_type = "isa";
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <0xf000 0 0 0 0>;
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ranges = <1 0 0x01000000 0 0
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0x00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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reg = <1 0x20 2
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1 0xa0 2
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1 0x4d0 2>;
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interrupt-controller;
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device_type = "interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <9 2 0 0>;
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};
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i8042@60 {
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#size-cells = <0>;
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#address-cells = <1>;
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reg = <1 0x60 1 1 0x64 1>;
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interrupts = <1 3 12 3>;
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interrupt-parent = <&i8259>;
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keyboard@0 {
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reg = <0>;
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compatible = "pnpPNP,303";
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};
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mouse@1 {
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reg = <1>;
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compatible = "pnpPNP,f03";
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};
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};
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rtc@70 {
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compatible =
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"pnpPNP,b00";
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reg = <1 0x70 2>;
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};
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gpio@400 {
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reg = <1 0x400 0x80>;
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};
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};
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};
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};
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};
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pci1: pcie@ffe09000 {
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reg = <0xffe09000 0x1000>;
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ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0x0 0xa0000000
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0x02000000 0x0 0xa0000000
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0x0 0x20000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00010000>;
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};
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};
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/*
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* Only one of Rapid IO or PCI can be present due to HW limitations and
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* due to the fact that the 2 now share address space in the new memory
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* map. The most likely case is that we have PCI, so comment out the
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* rapidio node. Leave it here for reference.
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rapidio@ffec0000 {
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reg = <0xffec0000 0x11000>;
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compatible = "fsl,srio";
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interrupts = <48 2 0 0>;
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#address-cells = <2>;
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#size-cells = <2>;
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fsl,srio-rmu-handle = <&rmu>;
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ranges;
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port1 {
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#address-cells = <2>;
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#size-cells = <2>;
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cell-index = <1>;
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ranges = <0 0 0x80000000 0 0x20000000>;
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};
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};
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*/
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};
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/include/ "mpc8641si-post.dtsi"
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@ -1,337 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC8641 HPCN Device Tree Source
|
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*
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* Copyright 2008-2009 Freescale Semiconductor Inc.
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*/
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|
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/include/ "mpc8641si-pre.dtsi"
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/ {
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model = "MPC8641HPCN";
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compatible = "fsl,mpc8641hpcn";
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#address-cells = <2>;
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#size-cells = <2>;
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memory {
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device_type = "memory";
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reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
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};
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lbc: localbus@fffe05000 {
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reg = <0x0f 0xffe05000 0x0 0x1000>;
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ranges = <0 0 0xf 0xef800000 0x00800000
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2 0 0xf 0xffdf8000 0x00008000
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3 0 0xf 0xffdf0000 0x00008000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x00800000>;
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bank-width = <2>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x00300000>;
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};
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partition@300000 {
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label = "firmware b";
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reg = <0x00300000 0x00100000>;
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read-only;
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};
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partition@400000 {
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label = "fs";
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reg = <0x00400000 0x00300000>;
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};
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partition@700000 {
|
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label = "firmware a";
|
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reg = <0x00700000 0x00100000>;
|
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read-only;
|
||||
};
|
||||
};
|
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};
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soc: soc8641@fffe00000 {
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ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
|
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|
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enet0: ethernet@24000 {
|
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tbi-handle = <&tbi0>;
|
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phy-handle = <&phy0>;
|
||||
phy-connection-type = "rgmii-id";
|
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};
|
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|
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mdio@24520 {
|
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phy0: ethernet-phy@0 {
|
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interrupts = <10 1 0 0>;
|
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reg = <0>;
|
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};
|
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phy1: ethernet-phy@1 {
|
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interrupts = <10 1 0 0>;
|
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reg = <1>;
|
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};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <2>;
|
||||
};
|
||||
phy3: ethernet-phy@3 {
|
||||
interrupts = <10 1 0 0>;
|
||||
reg = <3>;
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
tbi-handle = <&tbi1>;
|
||||
phy-handle = <&phy1>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@25520 {
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet2: ethernet@26000 {
|
||||
tbi-handle = <&tbi2>;
|
||||
phy-handle = <&phy2>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@26520 {
|
||||
tbi2: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
|
||||
enet3: ethernet@27000 {
|
||||
tbi-handle = <&tbi3>;
|
||||
phy-handle = <&phy3>;
|
||||
phy-connection-type = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@27520 {
|
||||
tbi3: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@fffe08000 {
|
||||
reg = <0x0f 0xffe08000 0x0 0x1000>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
|
||||
interrupt-map-mask = <0xff00 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x11 func 0 - PCI slot 1 */
|
||||
0x8800 0 0 1 &mpic 2 1 0 0
|
||||
0x8800 0 0 2 &mpic 3 1 0 0
|
||||
0x8800 0 0 3 &mpic 4 1 0 0
|
||||
0x8800 0 0 4 &mpic 1 1 0 0
|
||||
|
||||
/* IDSEL 0x11 func 1 - PCI slot 1 */
|
||||
0x8900 0 0 1 &mpic 2 1 0 0
|
||||
0x8900 0 0 2 &mpic 3 1 0 0
|
||||
0x8900 0 0 3 &mpic 4 1 0 0
|
||||
0x8900 0 0 4 &mpic 1 1 0 0
|
||||
|
||||
/* IDSEL 0x11 func 2 - PCI slot 1 */
|
||||
0x8a00 0 0 1 &mpic 2 1 0 0
|
||||
0x8a00 0 0 2 &mpic 3 1 0 0
|
||||
0x8a00 0 0 3 &mpic 4 1 0 0
|
||||
0x8a00 0 0 4 &mpic 1 1 0 0
|
||||
|
||||
/* IDSEL 0x11 func 3 - PCI slot 1 */
|
||||
0x8b00 0 0 1 &mpic 2 1 0 0
|
||||
0x8b00 0 0 2 &mpic 3 1 0 0
|
||||
0x8b00 0 0 3 &mpic 4 1 0 0
|
||||
0x8b00 0 0 4 &mpic 1 1 0 0
|
||||
|
||||
/* IDSEL 0x11 func 4 - PCI slot 1 */
|
||||
0x8c00 0 0 1 &mpic 2 1 0 0
|
||||
0x8c00 0 0 2 &mpic 3 1 0 0
|
||||
0x8c00 0 0 3 &mpic 4 1 0 0
|
||||
0x8c00 0 0 4 &mpic 1 1 0 0
|
||||
|
||||
/* IDSEL 0x11 func 5 - PCI slot 1 */
|
||||
0x8d00 0 0 1 &mpic 2 1 0 0
|
||||
0x8d00 0 0 2 &mpic 3 1 0 0
|
||||
0x8d00 0 0 3 &mpic 4 1 0 0
|
||||
0x8d00 0 0 4 &mpic 1 1 0 0
|
||||
|
||||
/* IDSEL 0x11 func 6 - PCI slot 1 */
|
||||
0x8e00 0 0 1 &mpic 2 1 0 0
|
||||
0x8e00 0 0 2 &mpic 3 1 0 0
|
||||
0x8e00 0 0 3 &mpic 4 1 0 0
|
||||
0x8e00 0 0 4 &mpic 1 1 0 0
|
||||
|
||||
/* IDSEL 0x11 func 7 - PCI slot 1 */
|
||||
0x8f00 0 0 1 &mpic 2 1 0 0
|
||||
0x8f00 0 0 2 &mpic 3 1 0 0
|
||||
0x8f00 0 0 3 &mpic 4 1 0 0
|
||||
0x8f00 0 0 4 &mpic 1 1 0 0
|
||||
|
||||
/* IDSEL 0x12 func 0 - PCI slot 2 */
|
||||
0x9000 0 0 1 &mpic 3 1 0 0
|
||||
0x9000 0 0 2 &mpic 4 1 0 0
|
||||
0x9000 0 0 3 &mpic 1 1 0 0
|
||||
0x9000 0 0 4 &mpic 2 1 0 0
|
||||
|
||||
/* IDSEL 0x12 func 1 - PCI slot 2 */
|
||||
0x9100 0 0 1 &mpic 3 1 0 0
|
||||
0x9100 0 0 2 &mpic 4 1 0 0
|
||||
0x9100 0 0 3 &mpic 1 1 0 0
|
||||
0x9100 0 0 4 &mpic 2 1 0 0
|
||||
|
||||
/* IDSEL 0x12 func 2 - PCI slot 2 */
|
||||
0x9200 0 0 1 &mpic 3 1 0 0
|
||||
0x9200 0 0 2 &mpic 4 1 0 0
|
||||
0x9200 0 0 3 &mpic 1 1 0 0
|
||||
0x9200 0 0 4 &mpic 2 1 0 0
|
||||
|
||||
/* IDSEL 0x12 func 3 - PCI slot 2 */
|
||||
0x9300 0 0 1 &mpic 3 1 0 0
|
||||
0x9300 0 0 2 &mpic 4 1 0 0
|
||||
0x9300 0 0 3 &mpic 1 1 0 0
|
||||
0x9300 0 0 4 &mpic 2 1 0 0
|
||||
|
||||
/* IDSEL 0x12 func 4 - PCI slot 2 */
|
||||
0x9400 0 0 1 &mpic 3 1 0 0
|
||||
0x9400 0 0 2 &mpic 4 1 0 0
|
||||
0x9400 0 0 3 &mpic 1 1 0 0
|
||||
0x9400 0 0 4 &mpic 2 1 0 0
|
||||
|
||||
/* IDSEL 0x12 func 5 - PCI slot 2 */
|
||||
0x9500 0 0 1 &mpic 3 1 0 0
|
||||
0x9500 0 0 2 &mpic 4 1 0 0
|
||||
0x9500 0 0 3 &mpic 1 1 0 0
|
||||
0x9500 0 0 4 &mpic 2 1 0 0
|
||||
|
||||
/* IDSEL 0x12 func 6 - PCI slot 2 */
|
||||
0x9600 0 0 1 &mpic 3 1 0 0
|
||||
0x9600 0 0 2 &mpic 4 1 0 0
|
||||
0x9600 0 0 3 &mpic 1 1 0 0
|
||||
0x9600 0 0 4 &mpic 2 1 0 0
|
||||
|
||||
/* IDSEL 0x12 func 7 - PCI slot 2 */
|
||||
0x9700 0 0 1 &mpic 3 1 0 0
|
||||
0x9700 0 0 2 &mpic 4 1 0 0
|
||||
0x9700 0 0 3 &mpic 1 1 0 0
|
||||
0x9700 0 0 4 &mpic 2 1 0 0
|
||||
|
||||
// IDSEL 0x1c USB
|
||||
0xe000 0 0 1 &i8259 12 2
|
||||
0xe100 0 0 2 &i8259 9 2
|
||||
0xe200 0 0 3 &i8259 10 2
|
||||
0xe300 0 0 4 &i8259 11 2
|
||||
|
||||
// IDSEL 0x1d Audio
|
||||
0xe800 0 0 1 &i8259 6 2
|
||||
|
||||
// IDSEL 0x1e Legacy
|
||||
0xf000 0 0 1 &i8259 7 2
|
||||
0xf100 0 0 1 &i8259 7 2
|
||||
|
||||
// IDSEL 0x1f IDE/SATA
|
||||
0xf800 0 0 1 &i8259 14 2
|
||||
0xf900 0 0 1 &i8259 5 2
|
||||
>;
|
||||
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0x0 0xe0000000
|
||||
0x02000000 0x0 0xe0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00010000>;
|
||||
uli1575@0 {
|
||||
reg = <0 0 0 0 0>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
ranges = <0x02000000 0x0 0xe0000000
|
||||
0x02000000 0x0 0xe0000000
|
||||
0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00010000>;
|
||||
isa@1e {
|
||||
device_type = "isa";
|
||||
#size-cells = <1>;
|
||||
#address-cells = <2>;
|
||||
reg = <0xf000 0 0 0 0>;
|
||||
ranges = <1 0 0x01000000 0 0
|
||||
0x00001000>;
|
||||
interrupt-parent = <&i8259>;
|
||||
|
||||
i8259: interrupt-controller@20 {
|
||||
reg = <1 0x20 2
|
||||
1 0xa0 2
|
||||
1 0x4d0 2>;
|
||||
interrupt-controller;
|
||||
device_type = "interrupt-controller";
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "chrp,iic";
|
||||
interrupts = <9 2 0 0>;
|
||||
};
|
||||
|
||||
i8042@60 {
|
||||
#size-cells = <0>;
|
||||
#address-cells = <1>;
|
||||
reg = <1 0x60 1 1 0x64 1>;
|
||||
interrupts = <1 3 12 3>;
|
||||
interrupt-parent = <&i8259>;
|
||||
|
||||
keyboard@0 {
|
||||
reg = <0>;
|
||||
compatible = "pnpPNP,303";
|
||||
};
|
||||
|
||||
mouse@1 {
|
||||
reg = <1>;
|
||||
compatible = "pnpPNP,f03";
|
||||
};
|
||||
};
|
||||
|
||||
rtc@70 {
|
||||
compatible =
|
||||
"pnpPNP,b00";
|
||||
reg = <1 0x70 2>;
|
||||
};
|
||||
|
||||
gpio@400 {
|
||||
reg = <1 0x400 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci1: pcie@fffe09000 {
|
||||
reg = <0x0f 0xffe09000 0x0 0x1000>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
|
||||
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0x0 0xe0000000
|
||||
0x02000000 0x0 0xe0000000
|
||||
0x0 0x20000000
|
||||
|
||||
0x01000000 0x0 0x00000000
|
||||
0x01000000 0x0 0x00000000
|
||||
0x0 0x00010000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "mpc8641si-post.dtsi"
|
||||
|
|
@ -1,5 +1,4 @@
|
|||
CONFIG_PPC_86xx=y
|
||||
CONFIG_MPC8641_HPCN=y
|
||||
CONFIG_MPC8610_HPCD=y
|
||||
CONFIG_GEF_PPC9A=y
|
||||
CONFIG_GEF_SBC310=y
|
||||
|
|
|
|||
|
|
@ -50,7 +50,6 @@ CONFIG_MPC836x_RDK=y
|
|||
CONFIG_MPC837x_RDB=y
|
||||
CONFIG_ASP834x=y
|
||||
CONFIG_PPC_86xx=y
|
||||
CONFIG_MPC8641_HPCN=y
|
||||
CONFIG_MPC8610_HPCD=y
|
||||
CONFIG_GEF_SBC610=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
|
|
|
|||
|
|
@ -10,16 +10,6 @@ menuconfig PPC_86xx
|
|||
|
||||
if PPC_86xx
|
||||
|
||||
config MPC8641_HPCN
|
||||
bool "Freescale MPC8641 HPCN"
|
||||
select PPC_I8259
|
||||
select DEFAULT_UIMAGE
|
||||
select FSL_ULI1575 if PCI
|
||||
select HAVE_RAPIDIO
|
||||
select SWIOTLB
|
||||
help
|
||||
This option enables support for the MPC8641 HPCN board.
|
||||
|
||||
config MPC8610_HPCD
|
||||
bool "Freescale MPC8610 HPCD"
|
||||
select DEFAULT_UIMAGE
|
||||
|
|
@ -68,7 +58,7 @@ config MPC8641
|
|||
select FSL_PCI if PCI
|
||||
select PPC_UDBG_16550
|
||||
select MPIC
|
||||
default y if MPC8641_HPCN || GEF_SBC610 || GEF_SBC310 || GEF_PPC9A \
|
||||
default y if GEF_SBC610 || GEF_SBC310 || GEF_PPC9A \
|
||||
|| MVME7100
|
||||
|
||||
config MPC8610
|
||||
|
|
|
|||
|
|
@ -5,7 +5,6 @@
|
|||
|
||||
obj-y := pic.o common.o
|
||||
obj-$(CONFIG_SMP) += mpc86xx_smp.o
|
||||
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
|
||||
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
|
||||
obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
|
||||
obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o
|
||||
|
|
|
|||
|
|
@ -1,98 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* MPC86xx HPCN board specific routines
|
||||
*
|
||||
* Recode: ZHANG WEI <wei.zhang@freescale.com>
|
||||
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
|
||||
*
|
||||
* Copyright 2006 Freescale Semiconductor Inc.
|
||||
*/
|
||||
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/of_platform.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/swiotlb.h>
|
||||
#include <asm/ppc-pci.h>
|
||||
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
|
||||
#include "mpc86xx.h"
|
||||
|
||||
#undef DEBUG
|
||||
|
||||
#ifdef DEBUG
|
||||
#define DBG(fmt...) do { printk(KERN_ERR fmt); } while(0)
|
||||
#else
|
||||
#define DBG(fmt...) do { } while(0)
|
||||
#endif
|
||||
|
||||
|
||||
static void __init
|
||||
mpc86xx_hpcn_setup_arch(void)
|
||||
{
|
||||
if (ppc_md.progress)
|
||||
ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
|
||||
|
||||
printk("MPC86xx HPCN board from Freescale Semiconductor\n");
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
mpc86xx_smp_init();
|
||||
#endif
|
||||
|
||||
fsl_pci_assign_primary();
|
||||
uli_init();
|
||||
|
||||
swiotlb_detect_4g();
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
|
||||
{
|
||||
uint svid = mfspr(SPRN_SVR);
|
||||
|
||||
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
|
||||
|
||||
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
|
||||
}
|
||||
|
||||
static const struct of_device_id of_bus_ids[] __initconst = {
|
||||
{ .compatible = "fsl,srio", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init declare_of_platform_devices(void)
|
||||
{
|
||||
mpc86xx_common_publish_devices();
|
||||
of_platform_bus_probe(NULL, of_bus_ids, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
machine_arch_initcall(mpc86xx_hpcn, declare_of_platform_devices);
|
||||
|
||||
define_machine(mpc86xx_hpcn) {
|
||||
.name = "MPC86xx HPCN",
|
||||
.compatible = "fsl,MPC8610HPCD",
|
||||
.setup_arch = mpc86xx_hpcn_setup_arch,
|
||||
.init_IRQ = mpc86xx_init_irq,
|
||||
.show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
|
||||
.get_irq = mpic_get_irq,
|
||||
.time_init = mpc86xx_time_init,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
};
|
||||
Loading…
Reference in New Issue