[ALSA] ASoC Samsung S3C24xx I2S support
This patch by Ben Dooks from Simtec Electronics adds ASoC I2S support for the Samsung S3C24xx CPU. Signed-off-by: Ben Dooks <ben@simtec.co.uk> Signed-off-by: Graeme Gregory <gg@opensource.wolfsonmicro.com> Signed-off-by: Liam Girdwood <lg@opensource.wolfsonmicro.com> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
This commit is contained in:
Ben Dooks
Jaroslav Kysela
parent
129a84de23
commit
c1422a6658
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@ -0,0 +1,439 @@
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/*
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* s3c24xx-i2s.c -- ALSA Soc Audio Layer
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*
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* (c) 2006 Wolfson Microelectronics PLC.
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* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
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*
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* (c) 2004-2005 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*
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* Revision history
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* 11th Dec 2006 Merged with Simtec driver
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* 10th Nov 2006 Initial version.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <sound/driver.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/regs-iis.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-clock.h>
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#include <asm/arch/audio.h>
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#include <asm/dma.h>
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#include <asm/arch/dma.h>
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#include "s3c24xx-pcm.h"
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#include "s3c24xx-i2s.h"
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#define S3C24XX_I2S_DEBUG 0
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#if S3C24XX_I2S_DEBUG
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#define DBG(x...) printk(KERN_DEBUG x)
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#else
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#define DBG(x...)
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#endif
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static struct s3c2410_dma_client s3c24xx_dma_client_out = {
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.name = "I2S PCM Stereo out"
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};
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static struct s3c2410_dma_client s3c24xx_dma_client_in = {
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.name = "I2S PCM Stereo in"
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
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.client = &s3c24xx_dma_client_out,
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.channel = DMACH_I2S_OUT,
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.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO
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};
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static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
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.client = &s3c24xx_dma_client_in,
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.channel = DMACH_I2S_IN,
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.dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO
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};
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struct s3c24xx_i2s_info {
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void __iomem *regs;
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struct clk *iis_clk;
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};
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static struct s3c24xx_i2s_info s3c24xx_i2s;
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static void s3c24xx_snd_txctrl(int on)
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{
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u32 iisfcon;
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u32 iiscon;
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u32 iismod;
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DBG("Entered %s\n", __FUNCTION__);
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iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
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if (on) {
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iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
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iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
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iiscon &= ~S3C2410_IISCON_TXIDLE;
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iismod |= S3C2410_IISMOD_TXMODE;
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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} else {
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/* note, we have to disable the FIFOs otherwise bad things
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* seem to happen when the DMA stops. According to the
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* Samsung supplied kernel, this should allow the DMA
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* engine and FIFOs to reset. If this isn't allowed, the
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* DMA engine will simply freeze randomly.
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*/
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iisfcon &= ~S3C2410_IISFCON_TXENABLE;
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iisfcon &= ~S3C2410_IISFCON_TXDMA;
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iiscon |= S3C2410_IISCON_TXIDLE;
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iiscon &= ~S3C2410_IISCON_TXDMAEN;
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iismod &= ~S3C2410_IISMOD_TXMODE;
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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}
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DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
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}
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static void s3c24xx_snd_rxctrl(int on)
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{
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u32 iisfcon;
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u32 iiscon;
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u32 iismod;
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DBG("Entered %s\n", __FUNCTION__);
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iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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DBG("r: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
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if (on) {
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iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
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iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
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iiscon &= ~S3C2410_IISCON_RXIDLE;
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iismod |= S3C2410_IISMOD_RXMODE;
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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} else {
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/* note, we have to disable the FIFOs otherwise bad things
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* seem to happen when the DMA stops. According to the
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* Samsung supplied kernel, this should allow the DMA
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* engine and FIFOs to reset. If this isn't allowed, the
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* DMA engine will simply freeze randomly.
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*/
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iisfcon &= ~S3C2410_IISFCON_RXENABLE;
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iisfcon &= ~S3C2410_IISFCON_RXDMA;
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iiscon |= S3C2410_IISCON_RXIDLE;
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iiscon &= ~S3C2410_IISCON_RXDMAEN;
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iismod &= ~S3C2410_IISMOD_RXMODE;
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writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
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writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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}
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DBG("w: IISCON: %lx IISMOD: %lx IISFCON: %lx\n", iiscon, iismod, iisfcon);
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}
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/*
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* Wait for the LR signal to allow synchronisation to the L/R clock
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* from the codec. May only be needed for slave mode.
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*/
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static int s3c24xx_snd_lrsync(void)
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{
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u32 iiscon;
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unsigned long timeout = jiffies + msecs_to_jiffies(5);
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DBG("Entered %s\n", __FUNCTION__);
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while (1) {
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iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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if (iiscon & S3C2410_IISCON_LRINDEX)
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break;
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if (timeout < jiffies)
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return -ETIMEDOUT;
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}
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return 0;
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}
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/*
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* Check whether CPU is the master or slave
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*/
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static inline int s3c24xx_snd_is_clkmaster(void)
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{
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DBG("Entered %s\n", __FUNCTION__);
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return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
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}
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/*
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* Set S3C24xx I2S DAI format
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*/
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static int s3c24xx_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
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unsigned int fmt)
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{
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u32 iismod;
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DBG("Entered %s\n", __FUNCTION__);
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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DBG("hw_params r: IISMOD: %lx \n", iismod);
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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iismod |= S3C2410_IISMOD_SLAVE;
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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break;
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default:
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return -EINVAL;
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}
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switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
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case SND_SOC_DAIFMT_LEFT_J:
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iismod |= S3C2410_IISMOD_MSB;
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break;
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case SND_SOC_DAIFMT_I2S:
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break;
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default:
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return -EINVAL;
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}
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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DBG("hw_params w: IISMOD: %lx \n", iismod);
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return 0;
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}
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static int s3c24xx_i2s_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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u32 iismod;
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DBG("Entered %s\n", __FUNCTION__);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
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else
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rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
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/* Working copies of register */
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iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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DBG("hw_params r: IISMOD: %lx\n", iismod);
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S8:
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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iismod |= S3C2410_IISMOD_16BIT;
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break;
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}
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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DBG("hw_params w: IISMOD: %lx\n", iismod);
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return 0;
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}
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static int s3c24xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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int ret = 0;
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DBG("Entered %s\n", __FUNCTION__);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (!s3c24xx_snd_is_clkmaster()) {
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ret = s3c24xx_snd_lrsync();
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if (ret)
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goto exit_err;
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}
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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s3c24xx_snd_rxctrl(1);
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else
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s3c24xx_snd_txctrl(1);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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s3c24xx_snd_rxctrl(0);
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else
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s3c24xx_snd_txctrl(0);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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exit_err:
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return ret;
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}
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/*
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* Set S3C24xx Clock source
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*/
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static int s3c24xx_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
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int clk_id, unsigned int freq, int dir)
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{
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u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
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DBG("Entered %s\n", __FUNCTION__);
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iismod &= ~S3C2440_IISMOD_MPLL;
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switch (clk_id) {
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case S3C24XX_CLKSRC_PCLK:
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break;
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case S3C24XX_CLKSRC_MPLL:
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iismod |= S3C2440_IISMOD_MPLL;
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break;
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default:
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return -EINVAL;
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}
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writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
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return 0;
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}
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/*
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* Set S3C24xx Clock dividers
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*/
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static int s3c24xx_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
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int div_id, int div)
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{
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u32 reg;
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DBG("Entered %s\n", __FUNCTION__);
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switch (div_id) {
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case S3C24XX_DIV_MCLK:
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reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
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writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
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break;
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case S3C24XX_DIV_BCLK:
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reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
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writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
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break;
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case S3C24XX_DIV_PRESCALER:
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writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
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reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
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writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* To avoid duplicating clock code, allow machine driver to
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* get the clockrate from here.
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*/
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u32 s3c24xx_i2s_get_clockrate(void)
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{
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return clk_get_rate(s3c24xx_i2s.iis_clk);
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}
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EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
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static int s3c24xx_i2s_probe(struct platform_device *pdev)
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{
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DBG("Entered %s\n", __FUNCTION__);
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s3c24xx_i2s.regs = ioremap(S3C2410_PA_IIS, 0x100);
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if (s3c24xx_i2s.regs == NULL)
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return -ENXIO;
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s3c24xx_i2s.iis_clk=clk_get(&pdev->dev, "iis");
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if (s3c24xx_i2s.iis_clk == NULL) {
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DBG("failed to get iis_clock\n");
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return -ENODEV;
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}
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clk_enable(s3c24xx_i2s.iis_clk);
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/* Configure the I2S pins in correct mode */
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s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
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s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
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s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
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s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
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s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
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writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
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s3c24xx_snd_txctrl(0);
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s3c24xx_snd_rxctrl(0);
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return 0;
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}
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#define S3C24XX_I2S_RATES \
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(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
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SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
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SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
|
||||
|
||||
struct snd_soc_cpu_dai s3c24xx_i2s_dai = {
|
||||
.name = "s3c24xx-i2s",
|
||||
.id = 0,
|
||||
.type = SND_SOC_DAI_I2S,
|
||||
.probe = s3c24xx_i2s_probe,
|
||||
.playback = {
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = S3C24XX_I2S_RATES,
|
||||
.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
|
||||
.capture = {
|
||||
.channels_min = 2,
|
||||
.channels_max = 2,
|
||||
.rates = S3C24XX_I2S_RATES,
|
||||
.formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE,},
|
||||
.ops = {
|
||||
.trigger = s3c24xx_i2s_trigger,
|
||||
.hw_params = s3c24xx_i2s_hw_params,},
|
||||
.dai_ops = {
|
||||
.set_fmt = s3c24xx_i2s_set_fmt,
|
||||
.set_clkdiv = s3c24xx_i2s_set_clkdiv,
|
||||
.set_sysclk = s3c24xx_i2s_set_sysclk,
|
||||
},
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(s3c24xx_i2s_dai);
|
||||
|
||||
/* Module information */
|
||||
MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
|
||||
MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* s3c24xx-i2s.c -- ALSA Soc Audio Layer
|
||||
*
|
||||
* Copyright 2005 Wolfson Microelectronics PLC.
|
||||
* Author: Graeme Gregory
|
||||
* graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* Revision history
|
||||
* 10th Nov 2006 Initial version.
|
||||
*/
|
||||
|
||||
#ifndef S3C24XXI2S_H_
|
||||
#define S3C24XXI2S_H_
|
||||
|
||||
/* clock sources */
|
||||
#define S3C24XX_CLKSRC_PCLK 0
|
||||
#define S3C24XX_CLKSRC_MPLL 1
|
||||
|
||||
/* Clock dividers */
|
||||
#define S3C24XX_DIV_MCLK 0
|
||||
#define S3C24XX_DIV_BCLK 1
|
||||
#define S3C24XX_DIV_PRESCALER 2
|
||||
|
||||
/* prescaler */
|
||||
#define S3C24XX_PRESCALE(a,b) \
|
||||
(((a - 1) << S3C2410_IISPSR_INTSHIFT) | ((b - 1) << S3C2410_IISPSR_EXTSHFIT))
|
||||
|
||||
u32 s3c24xx_i2s_get_clockrate(void);
|
||||
|
||||
#endif /*S3C24XXI2S_H_*/
|
||||
Loading…
Reference in New Issue