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Reset controller updates for v5.16 

Allow building the reset-brcmstb-rescal driver as module, add reset
 lines for the Uniphier PXs3 audio and video input subsystems and
 bindings for the Uniphier NX1 SoC, and add lan966x switch reset support
 to the reset-microchip-sparx5 driver.
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Merge tag 'reset-for-v5.16' of git://git.pengutronix.de/pza/linux into arm/drivers

Reset controller updates for v5.16

Allow building the reset-brcmstb-rescal driver as module, add reset
lines for the Uniphier PXs3 audio and video input subsystems and
bindings for the Uniphier NX1 SoC, and add lan966x switch reset support
to the reset-microchip-sparx5 driver.

* tag 'reset-for-v5.16' of git://git.pengutronix.de/pza/linux:
  reset: mchp: sparx5: Extend support for lan966x
  dt-bindings: reset: Add lan966x support
  reset: uniphier: Add NX1 reset support
  dt-bindings: reset: uniphier: Add NX1 reset control binding
  reset: uniphier: Add audio system and video input reset control for PXs3
  reset: Allow building Broadcom STB RESCAL as module

Link: https://lore.kernel.org/r/96e686f78f0e42bad666df5ec0cbcb2dcdc270a3.camel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2021-10-20 23:26:52 +02:00
parent 20f6d9586e 8c81620ac1
commit c13d33985d
7 changed files with 72 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/reset/microchip,rst.yaml
View File

@ -20,7 +20,9 @@ properties:
pattern: "^reset-controller@[0-9a-f]+$"
compatible:
const: microchip,sparx5-switch-reset
enum:
- microchip,sparx5-switch-reset
- microchip,lan966x-switch-reset
reg:
items:

1
Documentation/devicetree/bindings/reset/socionext,uniphier-glue-reset.yaml
View File

@ -23,6 +23,7 @@ properties:
- socionext,uniphier-pxs2-usb3-reset
- socionext,uniphier-ld20-usb3-reset
- socionext,uniphier-pxs3-usb3-reset
- socionext,uniphier-nx1-usb3-reset
- socionext,uniphier-pro4-ahci-reset
- socionext,uniphier-pxs2-ahci-reset
- socionext,uniphier-pxs3-ahci-reset

3
Documentation/devicetree/bindings/reset/socionext,uniphier-reset.yaml
View File

@ -23,6 +23,7 @@ properties:
- socionext,uniphier-ld11-reset
- socionext,uniphier-ld20-reset
- socionext,uniphier-pxs3-reset
- socionext,uniphier-nx1-reset
- description: Media I/O (MIO) reset, SD reset
enum:
- socionext,uniphier-ld4-mio-reset
@ -34,6 +35,7 @@ properties:
- socionext,uniphier-ld11-sd-reset
- socionext,uniphier-ld20-sd-reset
- socionext,uniphier-pxs3-sd-reset
- socionext,uniphier-nx1-sd-reset
- description: Peripheral reset
enum:
- socionext,uniphier-ld4-peri-reset
@ -44,6 +46,7 @@ properties:
- socionext,uniphier-ld11-peri-reset
- socionext,uniphier-ld20-peri-reset
- socionext,uniphier-pxs3-peri-reset
- socionext,uniphier-nx1-peri-reset
- description: Analog signal amplifier reset
enum:
- socionext,uniphier-ld11-adamv-reset

4
drivers/reset/Kconfig
View File

@ -58,7 +58,7 @@ config RESET_BRCMSTB
a SUN_TOP_CTRL_SW_INIT style controller.
config RESET_BRCMSTB_RESCAL
bool "Broadcom STB RESCAL reset controller"
tristate "Broadcom STB RESCAL reset controller"
depends on HAS_IOMEM
depends on ARCH_BRCMSTB || COMPILE_TEST
default ARCH_BRCMSTB
@ -116,7 +116,7 @@ config RESET_LPC18XX
config RESET_MCHP_SPARX5
bool "Microchip Sparx5 reset driver"
depends on ARCH_SPARX5 || COMPILE_TEST
depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
default y if SPARX5_SWITCH
select MFD_SYSCON
help

40
drivers/reset/reset-microchip-sparx5.c
View File

@ -13,15 +13,18 @@
#include <linux/regmap.h>
#include <linux/reset-controller.h>
#define PROTECT_REG 0x84
#define PROTECT_BIT BIT(10)
#define SOFT_RESET_REG 0x00
#define SOFT_RESET_BIT BIT(1)
struct reset_props {
u32 protect_reg;
u32 protect_bit;
u32 reset_reg;
u32 reset_bit;
};
struct mchp_reset_context {
struct regmap *cpu_ctrl;
struct regmap *gcb_ctrl;
struct reset_controller_dev rcdev;
const struct reset_props *props;
};
static struct regmap_config sparx5_reset_regmap_config = {
@ -38,14 +41,16 @@ static int sparx5_switch_reset(struct reset_controller_dev *rcdev,
u32 val;
/* Make sure the core is PROTECTED from reset */
regmap_update_bits(ctx->cpu_ctrl, PROTECT_REG, PROTECT_BIT, PROTECT_BIT);
regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg,
ctx->props->protect_bit, ctx->props->protect_bit);
/* Start soft reset */
regmap_write(ctx->gcb_ctrl, SOFT_RESET_REG, SOFT_RESET_BIT);
regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg,
ctx->props->reset_bit);
/* Wait for soft reset done */
return regmap_read_poll_timeout(ctx->gcb_ctrl, SOFT_RESET_REG, val,
(val & SOFT_RESET_BIT) == 0,
return regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val,
(val & ctx->props->reset_bit) == 0,
1, 100);
}
@ -115,13 +120,32 @@ static int mchp_sparx5_reset_probe(struct platform_device *pdev)
ctx->rcdev.nr_resets = 1;
ctx->rcdev.ops = &sparx5_reset_ops;
ctx->rcdev.of_node = dn;
ctx->props = device_get_match_data(&pdev->dev);
return devm_reset_controller_register(&pdev->dev, &ctx->rcdev);
}
static const struct reset_props reset_props_sparx5 = {
.protect_reg = 0x84,
.protect_bit = BIT(10),
.reset_reg = 0x0,
.reset_bit = BIT(1),
};
static const struct reset_props reset_props_lan966x = {
.protect_reg = 0x88,
.protect_bit = BIT(5),
.reset_reg = 0x0,
.reset_bit = BIT(1),
};
static const struct of_device_id mchp_sparx5_reset_of_match[] = {
{
.compatible = "microchip,sparx5-switch-reset",
.data = &reset_props_sparx5,
}, {
.compatible = "microchip,lan966x-switch-reset",
.data = &reset_props_lan966x,
},
{ }
};

4
drivers/reset/reset-uniphier-glue.c
View File

@ -155,6 +155,10 @@ static const struct of_device_id uniphier_glue_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-usb3-reset",
.data = &uniphier_pxs2_data,
},
{
.compatible = "socionext,uniphier-nx1-usb3-reset",
.data = &uniphier_pxs2_data,
},
{
.compatible = "socionext,uniphier-pro4-ahci-reset",
.data = &uniphier_pro4_data,

27
drivers/reset/reset-uniphier.c
View File

@ -136,6 +136,21 @@ static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
UNIPHIER_RESETX(28, 0x200c, 7), /* SATA0 */
UNIPHIER_RESETX(29, 0x200c, 8), /* SATA1 */
UNIPHIER_RESETX(30, 0x200c, 21), /* SATA-PHY */
UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
UNIPHIER_RESETX(42, 0x2010, 2), /* EXIV */
UNIPHIER_RESET_END,
};
static const struct uniphier_reset_data uniphier_nx1_sys_reset_data[] = {
UNIPHIER_RESETX(4, 0x2008, 8), /* eMMC */
UNIPHIER_RESETX(6, 0x200c, 0), /* Ether */
UNIPHIER_RESETX(12, 0x200c, 16), /* USB30 link */
UNIPHIER_RESETX(16, 0x200c, 24), /* USB30-PHY0 */
UNIPHIER_RESETX(17, 0x200c, 25), /* USB30-PHY1 */
UNIPHIER_RESETX(18, 0x200c, 26), /* USB30-PHY2 */
UNIPHIER_RESETX(24, 0x200c, 8), /* PCIe */
UNIPHIER_RESETX(52, 0x2010, 0), /* VOC */
UNIPHIER_RESETX(58, 0x2010, 8), /* HDMI-Tx */
UNIPHIER_RESET_END,
};
@ -400,6 +415,10 @@ static const struct of_device_id uniphier_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-reset",
.data = uniphier_pxs3_sys_reset_data,
},
{
.compatible = "socionext,uniphier-nx1-reset",
.data = uniphier_nx1_sys_reset_data,
},
/* Media I/O reset, SD reset */
{
.compatible = "socionext,uniphier-ld4-mio-reset",
@ -437,6 +456,10 @@ static const struct of_device_id uniphier_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-sd-reset",
.data = uniphier_pro5_sd_reset_data,
},
{
.compatible = "socionext,uniphier-nx1-sd-reset",
.data = uniphier_pro5_sd_reset_data,
},
/* Peripheral reset */
{
.compatible = "socionext,uniphier-ld4-peri-reset",
@ -470,6 +493,10 @@ static const struct of_device_id uniphier_reset_match[] = {
.compatible = "socionext,uniphier-pxs3-peri-reset",
.data = uniphier_pro4_peri_reset_data,
},
{
.compatible = "socionext,uniphier-nx1-peri-reset",
.data = uniphier_pro4_peri_reset_data,
},
/* Analog signal amplifiers reset */
{
.compatible = "socionext,uniphier-ld11-adamv-reset",