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Merge branches 'devel-gpmc' and 'devel-misc' into omap-for-linus

This commit is contained in:
Tony Lindgren 2010-12-22 11:30:12 -08:00
parent 4931445b94 da1f026b53
commit c10abbb265
237 changed files with 5100 additions and 3125 deletions
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25
Documentation/arm/OMAP/omap_pm
View File

@ -127,3 +127,28 @@ implementation needs:
10. (*pdata->cpu_set_freq)(unsigned long f)
11. (*pdata->cpu_get_freq)(void)
Customizing OPP for platform
============================
Defining CONFIG_PM should enable OPP layer for the silicon
and the registration of OPP table should take place automatically.
However, in special cases, the default OPP table may need to be
tweaked, for e.g.:
* enable default OPPs which are disabled by default, but which
could be enabled on a platform
* Disable an unsupported OPP on the platform
* Define and add a custom opp table entry
in these cases, the board file needs to do additional steps as follows:
arch/arm/mach-omapx/board-xyz.c
#include "pm.h"
....
static void __init omap_xyz_init_irq(void)
{
....
/* Initialize the default table */
omapx_opp_init();
/* Do customization to the defaults */
....
}
NOTE: omapx_opp_init will be omap3_opp_init or as required
based on the omap family.

5
Documentation/kernel-parameters.txt
View File

@ -2175,11 +2175,6 @@ and is between 256 and 4096 characters. It is defined in the file
reset_devices [KNL] Force drivers to reset the underlying device
during initialization.
resource_alloc_from_bottom
Allocate new resources from the beginning of available
space, not the end. If you need to use this, please
report a bug.
resume= [SWSUSP]
Specify the partition device for software suspend

4
Documentation/power/runtime_pm.txt
View File

@ -379,8 +379,8 @@ drivers/base/power/runtime.c and include/linux/pm_runtime.h:
zero)
bool pm_runtime_suspended(struct device *dev);
- return true if the device's runtime PM status is 'suspended', or false
otherwise
- return true if the device's runtime PM status is 'suspended' and its
'power.disable_depth' field is equal to zero, or false otherwise
void pm_runtime_allow(struct device *dev);
- set the power.runtime_auto flag for the device and decrease its usage

2
Makefile
View File

@ -1,7 +1,7 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 37
EXTRAVERSION = -rc6
EXTRAVERSION = -rc7
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*

2
arch/arm/mach-at91/Makefile
View File

@ -65,7 +65,7 @@ obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o
obj-$(CONFIG_MACH_PCONTROL_G20) += board-pcontrol-g20.o board-stamp9g20.o
# AT91SAM9260/AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o

98
arch/arm/mach-at91/board-pcontrol-g20.c
View File

@ -31,6 +31,7 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <mach/stamp9g20.h>
#include "sam9_smc.h"
#include "generic.h"
@ -38,11 +39,7 @@
static void __init pcontrol_g20_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
/* DGBU on ttyS0. (Rx, Tx) only TTL -> JTAG connector X7 17,19 ) */
at91_register_uart(0, 0, 0);
stamp9g20_map_io();
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS) piggyback A2 */
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS
@ -54,9 +51,6 @@ static void __init pcontrol_g20_map_io(void)
/* USART2 on ttyS3. (Rx, Tx) 9bit-Bus Multidrop-mode X4 */
at91_register_uart(AT91SAM9260_ID_US4, 3, 0);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
@ -66,38 +60,6 @@ static void __init init_irq(void)
}
/*
* NAND flash 512MiB 1,8V 8-bit, sector size 128 KiB
*/
static struct atmel_nand_data __initdata nand_data = {
.ale = 21,
.cle = 22,
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
};
/*
* Bus timings; unit = 7.57ns
*/
static struct sam9_smc_config __initdata nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 2,
.ncs_write_setup = 0,
.nwe_setup = 2,
.ncs_read_pulse = 4,
.nrd_pulse = 4,
.ncs_write_pulse = 4,
.nwe_pulse = 4,
.read_cycle = 7,
.write_cycle = 7,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
| AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
.tdf_cycles = 3,
};
static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
.ncs_read_setup = 16,
.nrd_setup = 18,
@ -138,14 +100,6 @@ static struct sam9_smc_config __initdata pcontrol_smc_config[2] = { {
.tdf_cycles = 1,
} };
static void __init add_device_nand(void)
{
/* configure chip-select 3 (NAND) */
sam9_smc_configure(3, &nand_smc_config);
at91_add_device_nand(&nand_data);
}
static void __init add_device_pcontrol(void)
{
/* configure chip-select 4 (IO compatible to 8051 X4 ) */
@ -155,23 +109,6 @@ static void __init add_device_pcontrol(void)
}
/*
* MCI (SD/MMC)
* det_pin, wp_pin and vcc_pin are not connected
*/
#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
static struct mci_platform_data __initdata mmc_data = {
.slot[0] = {
.bus_width = 4,
},
};
#else
static struct at91_mmc_data __initdata mmc_data = {
.wire4 = 1,
};
#endif
/*
* USB Host port
*/
@ -265,42 +202,13 @@ static struct spi_board_info pcontrol_g20_spi_devices[] = {
};
/*
* Dallas 1-Wire DS2431
*/
static struct w1_gpio_platform_data w1_gpio_pdata = {
.pin = AT91_PIN_PA29,
.is_open_drain = 1,
};
static struct platform_device w1_device = {
.name = "w1-gpio",
.id = -1,
.dev.platform_data = &w1_gpio_pdata,
};
static void add_wire1(void)
{
at91_set_GPIO_periph(w1_gpio_pdata.pin, 1);
at91_set_multi_drive(w1_gpio_pdata.pin, 1);
platform_device_register(&w1_device);
}
static void __init pcontrol_g20_board_init(void)
{
at91_add_device_serial();
add_device_nand();
#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
at91_add_device_mci(0, &mmc_data);
#else
at91_add_device_mmc(0, &mmc_data);
#endif
stamp9g20_board_init();
at91_add_device_usbh(&usbh_data);
at91_add_device_eth(&macb_data);
at91_add_device_i2c(pcontrol_g20_i2c_devices,
ARRAY_SIZE(pcontrol_g20_i2c_devices));
add_wire1();
add_device_pcontrol();
at91_add_device_spi(pcontrol_g20_spi_devices,
ARRAY_SIZE(pcontrol_g20_spi_devices));

82
arch/arm/mach-at91/board-stamp9g20.c
View File

@ -32,7 +32,7 @@
#include "generic.h"
static void __init portuxg20_map_io(void)
void __init stamp9g20_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
@ -40,6 +40,24 @@ static void __init portuxg20_map_io(void)
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init stamp9g20evb_map_io(void)
{
stamp9g20_map_io();
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR
| ATMEL_UART_DCD | ATMEL_UART_RI);
}
static void __init portuxg20_map_io(void)
{
stamp9g20_map_io();
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR
@ -56,26 +74,6 @@ static void __init portuxg20_map_io(void)
/* USART5 on ttyS6. (Rx, Tx only) */
at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init stamp9g20_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR
| ATMEL_UART_DCD | ATMEL_UART_RI);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init init_irq(void)
@ -156,7 +154,7 @@ static struct at91_udc_data __initdata portuxg20_udc_data = {
.pullup_pin = 0, /* pull-up driven by UDC */
};
static struct at91_udc_data __initdata stamp9g20_udc_data = {
static struct at91_udc_data __initdata stamp9g20evb_udc_data = {
.vbus_pin = AT91_PIN_PA22,
.pullup_pin = 0, /* pull-up driven by UDC */
};
@ -190,7 +188,7 @@ static struct gpio_led portuxg20_leds[] = {
}
};
static struct gpio_led stamp9g20_leds[] = {
static struct gpio_led stamp9g20evb_leds[] = {
{
.name = "D8",
.gpio = AT91_PIN_PB18,
@ -250,7 +248,7 @@ void add_w1(void)
}
static void __init generic_board_init(void)
void __init stamp9g20_board_init(void)
{
/* Serial */
at91_add_device_serial();
@ -262,34 +260,40 @@ static void __init generic_board_init(void)
#else
at91_add_device_mmc(0, &mmc_data);
#endif
/* USB Host */
at91_add_device_usbh(&usbh_data);
/* Ethernet */
at91_add_device_eth(&macb_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* W1 */
add_w1();
}
static void __init portuxg20_board_init(void)
{
generic_board_init();
/* SPI */
at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
stamp9g20_board_init();
/* USB Host */
at91_add_device_usbh(&usbh_data);
/* USB Device */
at91_add_device_udc(&portuxg20_udc_data);
/* Ethernet */
at91_add_device_eth(&macb_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* SPI */
at91_add_device_spi(portuxg20_spi_devices, ARRAY_SIZE(portuxg20_spi_devices));
/* LEDs */
at91_gpio_leds(portuxg20_leds, ARRAY_SIZE(portuxg20_leds));
}
static void __init stamp9g20_board_init(void)
static void __init stamp9g20evb_board_init(void)
{
generic_board_init();
stamp9g20_board_init();
/* USB Host */
at91_add_device_usbh(&usbh_data);
/* USB Device */
at91_add_device_udc(&stamp9g20_udc_data);
at91_add_device_udc(&stamp9g20evb_udc_data);
/* Ethernet */
at91_add_device_eth(&macb_data);
/* I2C */
at91_add_device_i2c(NULL, 0);
/* LEDs */
at91_gpio_leds(stamp9g20_leds, ARRAY_SIZE(stamp9g20_leds));
at91_gpio_leds(stamp9g20evb_leds, ARRAY_SIZE(stamp9g20evb_leds));
}
MACHINE_START(PORTUXG20, "taskit PortuxG20")
@ -305,7 +309,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
/* Maintainer: taskit GmbH */
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = stamp9g20_map_io,
.map_io = stamp9g20evb_map_io,
.init_irq = init_irq,
.init_machine = stamp9g20_board_init,
.init_machine = stamp9g20evb_board_init,
MACHINE_END

2
arch/arm/mach-at91/clock.c
View File

@ -658,7 +658,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
/* Now set uhpck values */
uhpck.parent = &utmi_clk;
uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
uhpck.rate_hz = utmi_clk.parent->rate_hz;
uhpck.rate_hz = utmi_clk.rate_hz;
uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
}

7
arch/arm/mach-at91/include/mach/stamp9g20.h Normal file
View File

@ -0,0 +1,7 @@
#ifndef __MACH_STAMP9G20_H
#define __MACH_STAMP9G20_H
void stamp9g20_map_io(void);
void stamp9g20_board_init(void);
#endif

2
arch/arm/mach-omap1/Makefile
View File

@ -3,7 +3,7 @@
#
# Common support
obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o
obj-y := io.o id.o sram.o irq.o mux.o flash.o serial.o devices.o dma.o
obj-y += clock.o clock_data.o opp_data.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o

124
arch/arm/mach-omap1/board-ams-delta.c
View File

@ -43,84 +43,82 @@
static u8 ams_delta_latch1_reg;
static u16 ams_delta_latch2_reg;
static int ams_delta_keymap[] = {
static const unsigned int ams_delta_keymap[] = {
KEY(0, 0, KEY_F1), /* Advert */
KEY(3, 0, KEY_COFFEE), /* Games */
KEY(2, 0, KEY_QUESTION), /* Directory */
KEY(3, 2, KEY_CONNECT), /* Internet */
KEY(2, 1, KEY_SHOP), /* Services */
KEY(0, 3, KEY_COFFEE), /* Games */
KEY(0, 2, KEY_QUESTION), /* Directory */
KEY(2, 3, KEY_CONNECT), /* Internet */
KEY(1, 2, KEY_SHOP), /* Services */
KEY(1, 1, KEY_PHONE), /* VoiceMail */
KEY(1, 0, KEY_DELETE), /* Delete */
KEY(0, 1, KEY_DELETE), /* Delete */
KEY(2, 2, KEY_PLAY), /* Play */
KEY(0, 1, KEY_PAGEUP), /* Up */
KEY(3, 1, KEY_PAGEDOWN), /* Down */
KEY(0, 2, KEY_EMAIL), /* ReadEmail */
KEY(1, 2, KEY_STOP), /* Stop */
KEY(1, 0, KEY_PAGEUP), /* Up */
KEY(1, 3, KEY_PAGEDOWN), /* Down */
KEY(2, 0, KEY_EMAIL), /* ReadEmail */
KEY(2, 1, KEY_STOP), /* Stop */
/* Numeric keypad portion */
KEY(7, 0, KEY_KP1),
KEY(6, 0, KEY_KP2),
KEY(5, 0, KEY_KP3),
KEY(7, 1, KEY_KP4),
KEY(6, 1, KEY_KP5),
KEY(5, 1, KEY_KP6),
KEY(7, 2, KEY_KP7),
KEY(6, 2, KEY_KP8),
KEY(5, 2, KEY_KP9),
KEY(6, 3, KEY_KP0),
KEY(7, 3, KEY_KPASTERISK),
KEY(5, 3, KEY_KPDOT), /* # key */
KEY(2, 7, KEY_NUMLOCK), /* Mute */
KEY(1, 7, KEY_KPMINUS), /* Recall */
KEY(1, 6, KEY_KPPLUS), /* Redial */
KEY(6, 7, KEY_KPSLASH), /* Handsfree */
KEY(0, 6, KEY_ENTER), /* Video */
KEY(0, 7, KEY_KP1),
KEY(0, 6, KEY_KP2),
KEY(0, 5, KEY_KP3),
KEY(1, 7, KEY_KP4),
KEY(1, 6, KEY_KP5),
KEY(1, 5, KEY_KP6),
KEY(2, 7, KEY_KP7),
KEY(2, 6, KEY_KP8),
KEY(2, 5, KEY_KP9),
KEY(3, 6, KEY_KP0),
KEY(3, 7, KEY_KPASTERISK),
KEY(3, 5, KEY_KPDOT), /* # key */
KEY(7, 2, KEY_NUMLOCK), /* Mute */
KEY(7, 1, KEY_KPMINUS), /* Recall */
KEY(6, 1, KEY_KPPLUS), /* Redial */
KEY(7, 6, KEY_KPSLASH), /* Handsfree */
KEY(6, 0, KEY_ENTER), /* Video */
KEY(4, 7, KEY_CAMERA), /* Photo */
KEY(7, 4, KEY_CAMERA), /* Photo */
KEY(4, 0, KEY_F2), /* Home */
KEY(4, 1, KEY_F3), /* Office */
KEY(4, 2, KEY_F4), /* Mobile */
KEY(0, 4, KEY_F2), /* Home */
KEY(1, 4, KEY_F3), /* Office */
KEY(2, 4, KEY_F4), /* Mobile */
KEY(7, 7, KEY_F5), /* SMS */
KEY(5, 7, KEY_F6), /* Email */
KEY(7, 5, KEY_F6), /* Email */
/* QWERTY portion of keypad */
KEY(4, 3, KEY_Q),
KEY(3, 4, KEY_Q),
KEY(3, 3, KEY_W),
KEY(2, 3, KEY_E),
KEY(1, 3, KEY_R),
KEY(0, 3, KEY_T),
KEY(7, 4, KEY_Y),
KEY(6, 4, KEY_U),
KEY(5, 4, KEY_I),
KEY(3, 2, KEY_E),
KEY(3, 1, KEY_R),
KEY(3, 0, KEY_T),
KEY(4, 7, KEY_Y),
KEY(4, 6, KEY_U),
KEY(4, 5, KEY_I),
KEY(4, 4, KEY_O),
KEY(3, 4, KEY_P),
KEY(4, 3, KEY_P),
KEY(2, 4, KEY_A),
KEY(1, 4, KEY_S),
KEY(0, 4, KEY_D),
KEY(7, 5, KEY_F),
KEY(6, 5, KEY_G),
KEY(4, 2, KEY_A),
KEY(4, 1, KEY_S),
KEY(4, 0, KEY_D),
KEY(5, 7, KEY_F),
KEY(5, 6, KEY_G),
KEY(5, 5, KEY_H),
KEY(4, 5, KEY_J),
KEY(3, 5, KEY_K),
KEY(2, 5, KEY_L),
KEY(5, 4, KEY_J),
KEY(5, 3, KEY_K),
KEY(5, 2, KEY_L),
KEY(1, 5, KEY_Z),
KEY(0, 5, KEY_X),
KEY(7, 6, KEY_C),
KEY(5, 1, KEY_Z),
KEY(5, 0, KEY_X),
KEY(6, 7, KEY_C),
KEY(6, 6, KEY_V),
KEY(5, 6, KEY_B),
KEY(4, 6, KEY_N),
KEY(3, 6, KEY_M),
KEY(2, 6, KEY_SPACE),
KEY(6, 5, KEY_B),
KEY(6, 4, KEY_N),
KEY(6, 3, KEY_M),
KEY(6, 2, KEY_SPACE),
KEY(0, 7, KEY_LEFTSHIFT), /* Vol up */
KEY(3, 7, KEY_LEFTCTRL), /* Vol down */
0
KEY(7, 0, KEY_LEFTSHIFT), /* Vol up */
KEY(7, 3, KEY_LEFTCTRL), /* Vol down */
};
void ams_delta_latch1_write(u8 mask, u8 value)
@ -189,11 +187,15 @@ static struct resource ams_delta_kp_resources[] = {
},
};
static const struct matrix_keymap_data ams_delta_keymap_data = {
.keymap = ams_delta_keymap,
.keymap_size = ARRAY_SIZE(ams_delta_keymap),
};
static struct omap_kp_platform_data ams_delta_kp_data = {
.rows = 8,
.cols = 8,
.keymap = ams_delta_keymap,
.keymapsize = ARRAY_SIZE(ams_delta_keymap),
.keymap_data = &ams_delta_keymap_data,
.delay = 9,
};

67
arch/arm/mach-omap1/board-fsample.c
View File

@ -69,36 +69,35 @@
#define fsample_cpld_clear(bit) \
fsample_cpld_write(0xf0 | ((bit) & 15), FSAMPLE_CPLD_SET_CLR)
static int fsample_keymap[] = {
KEY(0,0,KEY_UP),
KEY(0,1,KEY_RIGHT),
KEY(0,2,KEY_LEFT),
KEY(0,3,KEY_DOWN),
KEY(0,4,KEY_ENTER),
KEY(1,0,KEY_F10),
KEY(1,1,KEY_SEND),
KEY(1,2,KEY_END),
KEY(1,3,KEY_VOLUMEDOWN),
KEY(1,4,KEY_VOLUMEUP),
KEY(1,5,KEY_RECORD),
KEY(2,0,KEY_F9),
KEY(2,1,KEY_3),
KEY(2,2,KEY_6),
KEY(2,3,KEY_9),
KEY(2,4,KEY_KPDOT),
KEY(3,0,KEY_BACK),
KEY(3,1,KEY_2),
KEY(3,2,KEY_5),
KEY(3,3,KEY_8),
KEY(3,4,KEY_0),
KEY(3,5,KEY_KPSLASH),
KEY(4,0,KEY_HOME),
KEY(4,1,KEY_1),
KEY(4,2,KEY_4),
KEY(4,3,KEY_7),
KEY(4,4,KEY_KPASTERISK),
KEY(4,5,KEY_POWER),
0
static const unsigned int fsample_keymap[] = {
KEY(0, 0, KEY_UP),
KEY(1, 0, KEY_RIGHT),
KEY(2, 0, KEY_LEFT),
KEY(3, 0, KEY_DOWN),
KEY(4, 0, KEY_ENTER),
KEY(0, 1, KEY_F10),
KEY(1, 1, KEY_SEND),
KEY(2, 1, KEY_END),
KEY(3, 1, KEY_VOLUMEDOWN),
KEY(4, 1, KEY_VOLUMEUP),
KEY(5, 1, KEY_RECORD),
KEY(0, 2, KEY_F9),
KEY(1, 2, KEY_3),
KEY(2, 2, KEY_6),
KEY(3, 2, KEY_9),
KEY(4, 2, KEY_KPDOT),
KEY(0, 3, KEY_BACK),
KEY(1, 3, KEY_2),
KEY(2, 3, KEY_5),
KEY(3, 3, KEY_8),
KEY(4, 3, KEY_0),
KEY(5, 3, KEY_KPSLASH),
KEY(0, 4, KEY_HOME),
KEY(1, 4, KEY_1),
KEY(2, 4, KEY_4),
KEY(3, 4, KEY_7),
KEY(4, 4, KEY_KPASTERISK),
KEY(5, 4, KEY_POWER),
};
static struct smc91x_platdata smc91x_info = {
@ -253,11 +252,15 @@ static struct resource kp_resources[] = {
},
};
static const struct matrix_keymap_data fsample_keymap_data = {
.keymap = fsample_keymap,
.keymap_size = ARRAY_SIZE(fsample_keymap),
};
static struct omap_kp_platform_data kp_data = {
.rows = 8,
.cols = 8,
.keymap = fsample_keymap,
.keymapsize = ARRAY_SIZE(fsample_keymap),
.keymap_data = &fsample_keymap_data,
.delay = 4,
};

75
arch/arm/mach-omap1/board-h2.c
View File

@ -52,43 +52,42 @@
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
#define OMAP1610_ETHR_START 0x04000300
static int h2_keymap[] = {
static const unsigned int h2_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_RIGHT),
KEY(0, 2, KEY_3),
KEY(0, 3, KEY_F10),
KEY(0, 4, KEY_F5),
KEY(0, 5, KEY_9),
KEY(1, 0, KEY_DOWN),
KEY(1, 0, KEY_RIGHT),
KEY(2, 0, KEY_3),
KEY(3, 0, KEY_F10),
KEY(4, 0, KEY_F5),
KEY(5, 0, KEY_9),
KEY(0, 1, KEY_DOWN),
KEY(1, 1, KEY_UP),
KEY(1, 2, KEY_2),
KEY(1, 3, KEY_F9),
KEY(1, 4, KEY_F7),
KEY(1, 5, KEY_0),
KEY(2, 0, KEY_ENTER),
KEY(2, 1, KEY_6),
KEY(2, 1, KEY_2),
KEY(3, 1, KEY_F9),
KEY(4, 1, KEY_F7),
KEY(5, 1, KEY_0),
KEY(0, 2, KEY_ENTER),
KEY(1, 2, KEY_6),
KEY(2, 2, KEY_1),
KEY(2, 3, KEY_F2),
KEY(2, 4, KEY_F6),
KEY(2, 5, KEY_HOME),
KEY(3, 0, KEY_8),
KEY(3, 1, KEY_5),
KEY(3, 2, KEY_F12),
KEY(3, 2, KEY_F2),
KEY(4, 2, KEY_F6),
KEY(5, 2, KEY_HOME),
KEY(0, 3, KEY_8),
KEY(1, 3, KEY_5),
KEY(2, 3, KEY_F12),
KEY(3, 3, KEY_F3),
KEY(3, 4, KEY_F8),
KEY(3, 5, KEY_END),
KEY(4, 0, KEY_7),
KEY(4, 1, KEY_4),
KEY(4, 2, KEY_F11),
KEY(4, 3, KEY_F1),
KEY(4, 3, KEY_F8),
KEY(5, 3, KEY_END),
KEY(0, 4, KEY_7),
KEY(1, 4, KEY_4),
KEY(2, 4, KEY_F11),
KEY(3, 4, KEY_F1),
KEY(4, 4, KEY_F4),
KEY(4, 5, KEY_ESC),
KEY(5, 0, KEY_F13),
KEY(5, 1, KEY_F14),
KEY(5, 2, KEY_F15),
KEY(5, 3, KEY_F16),
KEY(5, 4, KEY_SLEEP),
0
KEY(5, 4, KEY_ESC),
KEY(0, 5, KEY_F13),
KEY(1, 5, KEY_F14),
KEY(2, 5, KEY_F15),
KEY(3, 5, KEY_F16),
KEY(4, 5, KEY_SLEEP),
};
static struct mtd_partition h2_nor_partitions[] = {
@ -270,14 +269,18 @@ static struct resource h2_kp_resources[] = {
},
};
static const struct matrix_keymap_data h2_keymap_data = {
.keymap = h2_keymap,
.keymap_size = ARRAY_SIZE(h2_keymap),
};
static struct omap_kp_platform_data h2_kp_data = {
.rows = 8,
.cols = 8,
.keymap = h2_keymap,
.keymapsize = ARRAY_SIZE(h2_keymap),
.rep = 1,
.keymap_data = &h2_keymap_data,
.rep = true,
.delay = 9,
.dbounce = 1,
.dbounce = true,
};
static struct platform_device h2_kp_device = {

75
arch/arm/mach-omap1/board-h3.c
View File

@ -56,43 +56,42 @@
#define H3_TS_GPIO 48
static int h3_keymap[] = {
static const unsigned int h3_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_RIGHT),
KEY(0, 2, KEY_3),
KEY(0, 3, KEY_F10),
KEY(0, 4, KEY_F5),
KEY(0, 5, KEY_9),
KEY(1, 0, KEY_DOWN),
KEY(1, 0, KEY_RIGHT),
KEY(2, 0, KEY_3),
KEY(3, 0, KEY_F10),
KEY(4, 0, KEY_F5),
KEY(5, 0, KEY_9),
KEY(0, 1, KEY_DOWN),
KEY(1, 1, KEY_UP),
KEY(1, 2, KEY_2),
KEY(1, 3, KEY_F9),
KEY(1, 4, KEY_F7),
KEY(1, 5, KEY_0),
KEY(2, 0, KEY_ENTER),
KEY(2, 1, KEY_6),
KEY(2, 1, KEY_2),
KEY(3, 1, KEY_F9),
KEY(4, 1, KEY_F7),
KEY(5, 1, KEY_0),
KEY(0, 2, KEY_ENTER),
KEY(1, 2, KEY_6),
KEY(2, 2, KEY_1),
KEY(2, 3, KEY_F2),
KEY(2, 4, KEY_F6),
KEY(2, 5, KEY_HOME),
KEY(3, 0, KEY_8),
KEY(3, 1, KEY_5),
KEY(3, 2, KEY_F12),
KEY(3, 2, KEY_F2),
KEY(4, 2, KEY_F6),
KEY(5, 2, KEY_HOME),
KEY(0, 3, KEY_8),
KEY(1, 3, KEY_5),
KEY(2, 3, KEY_F12),
KEY(3, 3, KEY_F3),
KEY(3, 4, KEY_F8),
KEY(3, 5, KEY_END),
KEY(4, 0, KEY_7),
KEY(4, 1, KEY_4),
KEY(4, 2, KEY_F11),
KEY(4, 3, KEY_F1),
KEY(4, 3, KEY_F8),
KEY(5, 3, KEY_END),
KEY(0, 4, KEY_7),
KEY(1, 4, KEY_4),
KEY(2, 4, KEY_F11),
KEY(3, 4, KEY_F1),
KEY(4, 4, KEY_F4),
KEY(4, 5, KEY_ESC),
KEY(5, 0, KEY_F13),
KEY(5, 1, KEY_F14),
KEY(5, 2, KEY_F15),
KEY(5, 3, KEY_F16),
KEY(5, 4, KEY_SLEEP),
0
KEY(5, 4, KEY_ESC),
KEY(0, 5, KEY_F13),
KEY(1, 5, KEY_F14),
KEY(2, 5, KEY_F15),
KEY(3, 5, KEY_F16),
KEY(4, 5, KEY_SLEEP),
};
@ -305,14 +304,18 @@ static struct resource h3_kp_resources[] = {
},
};
static const struct matrix_keymap_data h3_keymap_data = {
.keymap = h3_keymap,
.keymap_size = ARRAY_SIZE(h3_keymap),
};
static struct omap_kp_platform_data h3_kp_data = {
.rows = 8,
.cols = 8,
.keymap = h3_keymap,
.keymapsize = ARRAY_SIZE(h3_keymap),
.rep = 1,
.keymap_data = &h3_keymap_data,
.rep = true,
.delay = 9,
.dbounce = 1,
.dbounce = true,
};
static struct platform_device h3_kp_device = {

98
arch/arm/mach-omap1/board-htcherald.c
View File

@ -180,64 +180,68 @@
/* Keyboard definition */
static int htc_herald_keymap[] = {
static const unsigned int htc_herald_keymap[] = {
KEY(0, 0, KEY_RECORD), /* Mail button */
KEY(0, 1, KEY_CAMERA), /* Camera */
KEY(0, 2, KEY_PHONE), /* Send key */
KEY(0, 3, KEY_VOLUMEUP), /* Volume up */
KEY(0, 4, KEY_F2), /* Right bar (landscape) */
KEY(0, 5, KEY_MAIL), /* Win key (portrait) */
KEY(0, 6, KEY_DIRECTORY), /* Right bar (protrait) */
KEY(1, 0, KEY_LEFTCTRL), /* Windows key */
KEY(1, 0, KEY_CAMERA), /* Camera */
KEY(2, 0, KEY_PHONE), /* Send key */
KEY(3, 0, KEY_VOLUMEUP), /* Volume up */
KEY(4, 0, KEY_F2), /* Right bar (landscape) */
KEY(5, 0, KEY_MAIL), /* Win key (portrait) */
KEY(6, 0, KEY_DIRECTORY), /* Right bar (protrait) */
KEY(0, 1, KEY_LEFTCTRL), /* Windows key */
KEY(1, 1, KEY_COMMA),
KEY(1, 2, KEY_M),
KEY(1, 3, KEY_K),
KEY(1, 4, KEY_SLASH), /* OK key */
KEY(1, 5, KEY_I),
KEY(1, 6, KEY_U),
KEY(2, 0, KEY_LEFTALT),
KEY(2, 1, KEY_TAB),
KEY(2, 1, KEY_M),
KEY(3, 1, KEY_K),
KEY(4, 1, KEY_SLASH), /* OK key */
KEY(5, 1, KEY_I),
KEY(6, 1, KEY_U),
KEY(0, 2, KEY_LEFTALT),
KEY(1, 2, KEY_TAB),
KEY(2, 2, KEY_N),
KEY(2, 3, KEY_J),
KEY(2, 4, KEY_ENTER),
KEY(2, 5, KEY_H),
KEY(2, 6, KEY_Y),
KEY(3, 0, KEY_SPACE),
KEY(3, 1, KEY_L),
KEY(3, 2, KEY_B),
KEY(3, 2, KEY_J),
KEY(4, 2, KEY_ENTER),
KEY(5, 2, KEY_H),
KEY(6, 2, KEY_Y),
KEY(0, 3, KEY_SPACE),
KEY(1, 3, KEY_L),
KEY(2, 3, KEY_B),
KEY(3, 3, KEY_V),
KEY(3, 4, KEY_BACKSPACE),
KEY(3, 5, KEY_G),
KEY(3, 6, KEY_T),
KEY(4, 0, KEY_CAPSLOCK), /* Shift */
KEY(4, 1, KEY_C),
KEY(4, 2, KEY_F),
KEY(4, 3, KEY_R),
KEY(4, 3, KEY_BACKSPACE),
KEY(5, 3, KEY_G),
KEY(6, 3, KEY_T),
KEY(0, 4, KEY_CAPSLOCK), /* Shift */
KEY(1, 4, KEY_C),
KEY(2, 4, KEY_F),
KEY(3, 4, KEY_R),
KEY(4, 4, KEY_O),
KEY(4, 5, KEY_E),
KEY(4, 6, KEY_D),
KEY(5, 0, KEY_X),
KEY(5, 1, KEY_Z),
KEY(5, 2, KEY_S),
KEY(5, 3, KEY_W),
KEY(5, 4, KEY_P),
KEY(5, 4, KEY_E),
KEY(6, 4, KEY_D),
KEY(0, 5, KEY_X),
KEY(1, 5, KEY_Z),
KEY(2, 5, KEY_S),
KEY(3, 5, KEY_W),
KEY(4, 5, KEY_P),
KEY(5, 5, KEY_Q),
KEY(5, 6, KEY_A),
KEY(6, 0, KEY_CONNECT), /* Voice button */
KEY(6, 2, KEY_CANCEL), /* End key */
KEY(6, 3, KEY_VOLUMEDOWN), /* Volume down */
KEY(6, 4, KEY_F1), /* Left bar (landscape) */
KEY(6, 5, KEY_WWW), /* OK button (portrait) */
KEY(6, 5, KEY_A),
KEY(0, 6, KEY_CONNECT), /* Voice button */
KEY(2, 6, KEY_CANCEL), /* End key */
KEY(3, 6, KEY_VOLUMEDOWN), /* Volume down */
KEY(4, 6, KEY_F1), /* Left bar (landscape) */
KEY(5, 6, KEY_WWW), /* OK button (portrait) */
KEY(6, 6, KEY_CALENDAR), /* Left bar (portrait) */
0
};
struct omap_kp_platform_data htcherald_kp_data = {
static const struct matrix_keymap_data htc_herald_keymap_data = {
.keymap = htc_herald_keymap,
.keymap_size = ARRAY_SIZE(htc_herald_keymap),
};
static struct omap_kp_platform_data htcherald_kp_data = {
.rows = 7,
.cols = 7,
.delay = 20,
.rep = 1,
.keymap = htc_herald_keymap,
.rep = true,
.keymap_data = &htc_herald_keymap_data,
};
static struct resource kp_resources[] = {
@ -278,7 +282,7 @@ static struct gpio_keys_button herald_gpio_keys_table[] = {
static struct gpio_keys_platform_data herald_gpio_keys_data = {
.buttons = herald_gpio_keys_table,
.nbuttons = ARRAY_SIZE(herald_gpio_keys_table),
.rep = 1,
.rep = true,
};
static struct platform_device herald_gpiokeys_device = {

21
arch/arm/mach-omap1/board-innovator.c
View File

@ -44,17 +44,16 @@
/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
#define INNOVATOR1610_ETHR_START 0x04000300
static int innovator_keymap[] = {
static const unsigned int innovator_keymap[] = {
KEY(0, 0, KEY_F1),
KEY(0, 3, KEY_DOWN),
KEY(3, 0, KEY_DOWN),
KEY(1, 1, KEY_F2),
KEY(1, 2, KEY_RIGHT),
KEY(2, 0, KEY_F3),
KEY(2, 1, KEY_F4),
KEY(2, 1, KEY_RIGHT),
KEY(0, 2, KEY_F3),
KEY(1, 2, KEY_F4),
KEY(2, 2, KEY_UP),
KEY(3, 2, KEY_ENTER),
KEY(2, 3, KEY_ENTER),
KEY(3, 3, KEY_LEFT),
0
};
static struct mtd_partition innovator_partitions[] = {
@ -126,11 +125,15 @@ static struct resource innovator_kp_resources[] = {
},
};
static const struct matrix_keymap_data innovator_keymap_data = {
.keymap = innovator_keymap,
.keymap_size = ARRAY_SIZE(innovator_keymap),
};
static struct omap_kp_platform_data innovator_kp_data = {
.rows = 8,
.cols = 8,
.keymap = innovator_keymap,
.keymapsize = ARRAY_SIZE(innovator_keymap),
.keymap_data = &innovator_keymap_data,
.delay = 4,
};

29
arch/arm/mach-omap1/board-nokia770.c
View File

@ -54,19 +54,18 @@ static void __init omap_nokia770_init_irq(void)
omap_init_irq();
}
static int nokia770_keymap[] = {
KEY(0, 1, GROUP_0 | KEY_UP),
KEY(0, 2, GROUP_1 | KEY_F5),
KEY(1, 0, GROUP_0 | KEY_LEFT),
static const unsigned int nokia770_keymap[] = {
KEY(1, 0, GROUP_0 | KEY_UP),
KEY(2, 0, GROUP_1 | KEY_F5),
KEY(0, 1, GROUP_0 | KEY_LEFT),
KEY(1, 1, GROUP_0 | KEY_ENTER),
KEY(1, 2, GROUP_0 | KEY_RIGHT),
KEY(2, 0, GROUP_1 | KEY_ESC),
KEY(2, 1, GROUP_0 | KEY_DOWN),
KEY(2, 1, GROUP_0 | KEY_RIGHT),
KEY(0, 2, GROUP_1 | KEY_ESC),
KEY(1, 2, GROUP_0 | KEY_DOWN),
KEY(2, 2, GROUP_1 | KEY_F4),
KEY(3, 0, GROUP_2 | KEY_F7),
KEY(3, 1, GROUP_2 | KEY_F8),
KEY(3, 2, GROUP_2 | KEY_F6),
0
KEY(0, 3, GROUP_2 | KEY_F7),
KEY(1, 3, GROUP_2 | KEY_F8),
KEY(2, 3, GROUP_2 | KEY_F6),
};
static struct resource nokia770_kp_resources[] = {
@ -77,11 +76,15 @@ static struct resource nokia770_kp_resources[] = {
},
};
static const struct matrix_keymap_data nokia770_keymap_data = {
.keymap = nokia770_keymap,
.keymap_size = ARRAY_SIZE(nokia770_keymap),
};
static struct omap_kp_platform_data nokia770_kp_data = {
.rows = 8,
.cols = 8,
.keymap = nokia770_keymap,
.keymapsize = ARRAY_SIZE(nokia770_keymap),
.keymap_data = &nokia770_keymap_data,
.delay = 4,
};

21
arch/arm/mach-omap1/board-osk.c
View File

@ -338,25 +338,28 @@ static struct i2c_board_info __initdata mistral_i2c_board_info[] = {
*/
};
static const int osk_keymap[] = {
static const unsigned int osk_keymap[] = {
/* KEY(col, row, code) */
KEY(0, 0, KEY_F1), /* SW4 */
KEY(0, 3, KEY_UP), /* (sw2/up) */
KEY(3, 0, KEY_UP), /* (sw2/up) */
KEY(1, 1, KEY_LEFTCTRL), /* SW5 */
KEY(1, 2, KEY_LEFT), /* (sw2/left) */
KEY(2, 0, KEY_SPACE), /* SW3 */
KEY(2, 1, KEY_ESC), /* SW6 */
KEY(2, 1, KEY_LEFT), /* (sw2/left) */
KEY(0, 2, KEY_SPACE), /* SW3 */
KEY(1, 2, KEY_ESC), /* SW6 */
KEY(2, 2, KEY_DOWN), /* (sw2/down) */
KEY(3, 2, KEY_ENTER), /* (sw2/select) */
KEY(2, 3, KEY_ENTER), /* (sw2/select) */
KEY(3, 3, KEY_RIGHT), /* (sw2/right) */
0
};
static const struct matrix_keymap_data osk_keymap_data = {
.keymap = osk_keymap,
.keymap_size = ARRAY_SIZE(osk_keymap),
};
static struct omap_kp_platform_data osk_kp_data = {
.rows = 8,
.cols = 8,
.keymap = (int *) osk_keymap,
.keymapsize = ARRAY_SIZE(osk_keymap),
.keymap_data = &osk_keymap_data,
.delay = 9,
};

28
arch/arm/mach-omap1/board-palmte.c
View File

@ -65,25 +65,29 @@ static void __init omap_palmte_init_irq(void)
omap_init_irq();
}
static const int palmte_keymap[] = {
static const unsigned int palmte_keymap[] = {
KEY(0, 0, KEY_F1), /* Calendar */
KEY(0, 1, KEY_F2), /* Contacts */
KEY(0, 2, KEY_F3), /* Tasks List */
KEY(0, 3, KEY_F4), /* Note Pad */
KEY(0, 4, KEY_POWER),
KEY(1, 0, KEY_LEFT),
KEY(1, 0, KEY_F2), /* Contacts */
KEY(2, 0, KEY_F3), /* Tasks List */
KEY(3, 0, KEY_F4), /* Note Pad */
KEY(4, 0, KEY_POWER),
KEY(0, 1, KEY_LEFT),
KEY(1, 1, KEY_DOWN),
KEY(1, 2, KEY_UP),
KEY(1, 3, KEY_RIGHT),
KEY(1, 4, KEY_ENTER),
0,
KEY(2, 1, KEY_UP),
KEY(3, 1, KEY_RIGHT),
KEY(4, 1, KEY_ENTER),
};
static const struct matrix_keymap_data palmte_keymap_data = {
.keymap = palmte_keymap,
.keymap_size = ARRAY_SIZE(palmte_keymap),
};
static struct omap_kp_platform_data palmte_kp_data = {
.rows = 8,
.cols = 8,
.keymap = (int *) palmte_keymap,
.rep = 1,
.keymap_data = &palmte_keymap_data,
.rep = true,
.delay = 12,
};

28
arch/arm/mach-omap1/board-palmtt.c
View File

@ -51,19 +51,18 @@
#define PALMTT_MMC_WP_GPIO 8
#define PALMTT_HDQ_GPIO 11
static int palmtt_keymap[] = {
static const unsigned int palmtt_keymap[] = {
KEY(0, 0, KEY_ESC),
KEY(0, 1, KEY_SPACE),
KEY(0, 2, KEY_LEFTCTRL),
KEY(0, 3, KEY_TAB),
KEY(0, 4, KEY_ENTER),
KEY(1, 0, KEY_LEFT),
KEY(1, 0, KEY_SPACE),
KEY(2, 0, KEY_LEFTCTRL),
KEY(3, 0, KEY_TAB),
KEY(4, 0, KEY_ENTER),
KEY(0, 1, KEY_LEFT),
KEY(1, 1, KEY_DOWN),
KEY(1, 2, KEY_UP),
KEY(1, 3, KEY_RIGHT),
KEY(2, 0, KEY_SLEEP),
KEY(2, 4, KEY_Y),
0
KEY(2, 1, KEY_UP),
KEY(3, 1, KEY_RIGHT),
KEY(0, 2, KEY_SLEEP),
KEY(4, 2, KEY_Y),
};
static struct mtd_partition palmtt_partitions[] = {
@ -136,10 +135,15 @@ static struct resource palmtt_kp_resources[] = {
},
};
static const struct matrix_keymap_data palmtt_keymap_data = {
.keymap = palmtt_keymap,
.keymap_size = ARRAY_SIZE(palmtt_keymap),
};
static struct omap_kp_platform_data palmtt_kp_data = {
.rows = 6,
.cols = 3,
.keymap = palmtt_keymap,
.keymap_data = &palmtt_keymap_data,
};
static struct platform_device palmtt_kp_device = {

30
arch/arm/mach-omap1/board-palmz71.c
View File

@ -64,26 +64,30 @@ omap_palmz71_init_irq(void)
omap_init_irq();
}
static int palmz71_keymap[] = {
static const unsigned int palmz71_keymap[] = {
KEY(0, 0, KEY_F1),
KEY(0, 1, KEY_F2),
KEY(0, 2, KEY_F3),
KEY(0, 3, KEY_F4),
KEY(0, 4, KEY_POWER),
KEY(1, 0, KEY_LEFT),
KEY(1, 0, KEY_F2),
KEY(2, 0, KEY_F3),
KEY(3, 0, KEY_F4),
KEY(4, 0, KEY_POWER),
KEY(0, 1, KEY_LEFT),
KEY(1, 1, KEY_DOWN),
KEY(1, 2, KEY_UP),
KEY(1, 3, KEY_RIGHT),
KEY(1, 4, KEY_ENTER),
KEY(2, 0, KEY_CAMERA),
0,
KEY(2, 1, KEY_UP),
KEY(3, 1, KEY_RIGHT),
KEY(4, 1, KEY_ENTER),
KEY(0, 2, KEY_CAMERA),
};
static const struct matrix_keymap_data palmz71_keymap_data = {
.keymap = palmz71_keymap,
.keymap_size = ARRAY_SIZE(palmz71_keymap),
};
static struct omap_kp_platform_data palmz71_kp_data = {
.rows = 8,
.cols = 8,
.keymap = palmz71_keymap,
.rep = 1,
.keymap_data = &palmz71_keymap_data,
.rep = true,
.delay = 80,
};

69
arch/arm/mach-omap1/board-perseus2.c
View File

@ -36,36 +36,35 @@
#include <plat/common.h>
#include <plat/board.h>
static int p2_keymap[] = {
KEY(0,0,KEY_UP),
KEY(0,1,KEY_RIGHT),
KEY(0,2,KEY_LEFT),
KEY(0,3,KEY_DOWN),
KEY(0,4,KEY_ENTER),
KEY(1,0,KEY_F10),
KEY(1,1,KEY_SEND),
KEY(1,2,KEY_END),
KEY(1,3,KEY_VOLUMEDOWN),
KEY(1,4,KEY_VOLUMEUP),
KEY(1,5,KEY_RECORD),
KEY(2,0,KEY_F9),
KEY(2,1,KEY_3),
KEY(2,2,KEY_6),
KEY(2,3,KEY_9),
KEY(2,4,KEY_KPDOT),
KEY(3,0,KEY_BACK),
KEY(3,1,KEY_2),
KEY(3,2,KEY_5),
KEY(3,3,KEY_8),
KEY(3,4,KEY_0),
KEY(3,5,KEY_KPSLASH),
KEY(4,0,KEY_HOME),
KEY(4,1,KEY_1),
KEY(4,2,KEY_4),
KEY(4,3,KEY_7),
KEY(4,4,KEY_KPASTERISK),
KEY(4,5,KEY_POWER),
0
static const unsigned int p2_keymap[] = {
KEY(0, 0, KEY_UP),
KEY(1, 0, KEY_RIGHT),
KEY(2, 0, KEY_LEFT),
KEY(3, 0, KEY_DOWN),
KEY(4, 0, KEY_ENTER),
KEY(0, 1, KEY_F10),
KEY(1, 1, KEY_SEND),
KEY(2, 1, KEY_END),
KEY(3, 1, KEY_VOLUMEDOWN),
KEY(4, 1, KEY_VOLUMEUP),
KEY(5, 1, KEY_RECORD),
KEY(0, 2, KEY_F9),
KEY(1, 2, KEY_3),
KEY(2, 2, KEY_6),
KEY(3, 2, KEY_9),
KEY(4, 2, KEY_KPDOT),
KEY(0, 3, KEY_BACK),
KEY(1, 3, KEY_2),
KEY(2, 3, KEY_5),
KEY(3, 3, KEY_8),
KEY(4, 3, KEY_0),
KEY(5, 3, KEY_KPSLASH),
KEY(0, 4, KEY_HOME),
KEY(1, 4, KEY_1),
KEY(2, 4, KEY_4),
KEY(3, 4, KEY_7),
KEY(4, 4, KEY_KPASTERISK),
KEY(5, 4, KEY_POWER),
};
static struct smc91x_platdata smc91x_info = {
@ -211,13 +210,17 @@ static struct resource kp_resources[] = {
},
};
static const struct matrix_keymap_data p2_keymap_data = {
.keymap = p2_keymap,
.keymap_size = ARRAY_SIZE(p2_keymap),
};
static struct omap_kp_platform_data kp_data = {
.rows = 8,
.cols = 8,
.keymap = p2_keymap,
.keymapsize = ARRAY_SIZE(p2_keymap),
.keymap_data = &p2_keymap_data,
.delay = 4,
.dbounce = 1,
.dbounce = true,
};
static struct platform_device kp_device = {

57
arch/arm/mach-omap1/board-sx1.c
View File

@ -164,36 +164,35 @@ EXPORT_SYMBOL(sx1_setusbpower);
/*----------- Keypad -------------------------*/
static int sx1_keymap[] = {
KEY(5, 3, GROUP_0 | 117), /* camera Qt::Key_F17 */
KEY(0, 4, GROUP_0 | 114), /* voice memo Qt::Key_F14 */
KEY(1, 4, GROUP_2 | 114), /* voice memo */
KEY(2, 4, GROUP_3 | 114), /* voice memo */
static const unsigned int sx1_keymap[] = {
KEY(3, 5, GROUP_0 | 117), /* camera Qt::Key_F17 */
KEY(4, 0, GROUP_0 | 114), /* voice memo Qt::Key_F14 */
KEY(4, 1, GROUP_2 | 114), /* voice memo */
KEY(4, 2, GROUP_3 | 114), /* voice memo */
KEY(0, 0, GROUP_1 | KEY_F12), /* red button Qt::Key_Hangup */
KEY(4, 3, GROUP_1 | KEY_LEFT),
KEY(2, 3, GROUP_1 | KEY_DOWN),
KEY(1, 3, GROUP_1 | KEY_RIGHT),
KEY(0, 3, GROUP_1 | KEY_UP),
KEY(3, 4, GROUP_1 | KEY_LEFT),
KEY(3, 2, GROUP_1 | KEY_DOWN),
KEY(3, 1, GROUP_1 | KEY_RIGHT),
KEY(3, 0, GROUP_1 | KEY_UP),
KEY(3, 3, GROUP_1 | KEY_POWER), /* joystick press or Qt::Key_Select */
KEY(5, 0, GROUP_1 | KEY_1),
KEY(4, 0, GROUP_1 | KEY_2),
KEY(3, 0, GROUP_1 | KEY_3),
KEY(3, 4, GROUP_1 | KEY_4),
KEY(0, 5, GROUP_1 | KEY_1),
KEY(0, 4, GROUP_1 | KEY_2),
KEY(0, 3, GROUP_1 | KEY_3),
KEY(4, 3, GROUP_1 | KEY_4),
KEY(4, 4, GROUP_1 | KEY_5),
KEY(5, 4, GROUP_1 | KEY_KPASTERISK),/* "*" */
KEY(4, 1, GROUP_1 | KEY_6),
KEY(5, 1, GROUP_1 | KEY_7),
KEY(3, 1, GROUP_1 | KEY_8),
KEY(3, 2, GROUP_1 | KEY_9),
KEY(5, 2, GROUP_1 | KEY_0),
KEY(4, 2, GROUP_1 | 113), /* # F13 Toggle input method Qt::Key_F13 */
KEY(0, 1, GROUP_1 | KEY_F11), /* green button Qt::Key_Call */
KEY(1, 2, GROUP_1 | KEY_YEN), /* left soft Qt::Key_Context1 */
KEY(4, 5, GROUP_1 | KEY_KPASTERISK),/* "*" */
KEY(1, 4, GROUP_1 | KEY_6),
KEY(1, 5, GROUP_1 | KEY_7),
KEY(1, 3, GROUP_1 | KEY_8),
KEY(2, 3, GROUP_1 | KEY_9),
KEY(2, 5, GROUP_1 | KEY_0),
KEY(2, 4, GROUP_1 | 113), /* # F13 Toggle input method Qt::Key_F13 */
KEY(1, 0, GROUP_1 | KEY_F11), /* green button Qt::Key_Call */
KEY(2, 1, GROUP_1 | KEY_YEN), /* left soft Qt::Key_Context1 */
KEY(2, 2, GROUP_1 | KEY_F8), /* right soft Qt::Key_Back */
KEY(2, 1, GROUP_1 | KEY_LEFTSHIFT), /* shift */
KEY(1, 2, GROUP_1 | KEY_LEFTSHIFT), /* shift */
KEY(1, 1, GROUP_1 | KEY_BACKSPACE), /* C (clear) */
KEY(0, 2, GROUP_1 | KEY_F7), /* menu Qt::Key_Menu */
0
KEY(2, 0, GROUP_1 | KEY_F7), /* menu Qt::Key_Menu */
};
static struct resource sx1_kp_resources[] = {
@ -204,11 +203,15 @@ static struct resource sx1_kp_resources[] = {
},
};
static const struct matrix_keymap_data sx1_keymap_data = {
.keymap = sx1_keymap,
.keymap_size = ARRAY_SIZE(sx1_keymap),
};
static struct omap_kp_platform_data sx1_kp_data = {
.rows = 6,
.cols = 6,
.keymap = sx1_keymap,
.keymapsize = ARRAY_SIZE(sx1_keymap),
.keymap_data = &sx1_keymap_data,
.delay = 80,
};

390
arch/arm/mach-omap1/dma.c Normal file
View File

@ -0,0 +1,390 @@
/*
* OMAP1/OMAP7xx - specific DMA driver
*
* Copyright (C) 2003 - 2008 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
* Graphics DMA and LCD DMA graphics tranformations
* by Imre Deak <imre.deak@nokia.com>
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Converted DMA library into platform driver
* - G, Manjunath Kondaiah <manjugk@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <plat/dma.h>
#include <plat/tc.h>
#include <plat/irqs.h>
#define OMAP1_DMA_BASE (0xfffed800)
#define OMAP1_LOGICAL_DMA_CH_COUNT 17
#define OMAP1_DMA_STRIDE 0x40
static u32 errata;
static u32 enable_1510_mode;
static u8 dma_stride;
static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
static u16 reg_map[] = {
[GCR] = 0x400,
[GSCR] = 0x404,
[GRST1] = 0x408,
[HW_ID] = 0x442,
[PCH2_ID] = 0x444,
[PCH0_ID] = 0x446,
[PCH1_ID] = 0x448,
[PCHG_ID] = 0x44a,
[PCHD_ID] = 0x44c,
[CAPS_0] = 0x44e,
[CAPS_1] = 0x452,
[CAPS_2] = 0x456,
[CAPS_3] = 0x458,
[CAPS_4] = 0x45a,
[PCH2_SR] = 0x460,
[PCH0_SR] = 0x480,
[PCH1_SR] = 0x482,
[PCHD_SR] = 0x4c0,
/* Common Registers */
[CSDP] = 0x00,
[CCR] = 0x02,
[CICR] = 0x04,
[CSR] = 0x06,
[CEN] = 0x10,
[CFN] = 0x12,
[CSFI] = 0x14,
[CSEI] = 0x16,
[CPC] = 0x18, /* 15xx only */
[CSAC] = 0x18,
[CDAC] = 0x1a,
[CDEI] = 0x1c,
[CDFI] = 0x1e,
[CLNK_CTRL] = 0x28,
/* Channel specific register offsets */
[CSSA] = 0x08,
[CDSA] = 0x0c,
[COLOR] = 0x20,
[CCR2] = 0x24,
[LCH_CTRL] = 0x2a,
};
static struct resource res[] __initdata = {
[0] = {
.start = OMAP1_DMA_BASE,
.end = OMAP1_DMA_BASE + SZ_2K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.name = "0",
.start = INT_DMA_CH0_6,
.flags = IORESOURCE_IRQ,
},
[2] = {
.name = "1",
.start = INT_DMA_CH1_7,
.flags = IORESOURCE_IRQ,
},
[3] = {
.name = "2",
.start = INT_DMA_CH2_8,
.flags = IORESOURCE_IRQ,
},
[4] = {
.name = "3",
.start = INT_DMA_CH3,
.flags = IORESOURCE_IRQ,
},
[5] = {
.name = "4",
.start = INT_DMA_CH4,
.flags = IORESOURCE_IRQ,
},
[6] = {
.name = "5",
.start = INT_DMA_CH5,
.flags = IORESOURCE_IRQ,
},
/* Handled in lcd_dma.c */
[7] = {
.name = "6",
.start = INT_1610_DMA_CH6,
.flags = IORESOURCE_IRQ,
},
/* irq's for omap16xx and omap7xx */
[8] = {
.name = "7",
.start = INT_1610_DMA_CH7,
.flags = IORESOURCE_IRQ,
},
[9] = {
.name = "8",
.start = INT_1610_DMA_CH8,
.flags = IORESOURCE_IRQ,
},
[10] = {
.name = "9",
.start = INT_1610_DMA_CH9,
.flags = IORESOURCE_IRQ,
},
[11] = {
.name = "10",
.start = INT_1610_DMA_CH10,
.flags = IORESOURCE_IRQ,
},
[12] = {
.name = "11",
.start = INT_1610_DMA_CH11,
.flags = IORESOURCE_IRQ,
},
[13] = {
.name = "12",
.start = INT_1610_DMA_CH12,
.flags = IORESOURCE_IRQ,
},
[14] = {
.name = "13",
.start = INT_1610_DMA_CH13,
.flags = IORESOURCE_IRQ,
},
[15] = {
.name = "14",
.start = INT_1610_DMA_CH14,
.flags = IORESOURCE_IRQ,
},
[16] = {
.name = "15",
.start = INT_1610_DMA_CH15,
.flags = IORESOURCE_IRQ,
},
[17] = {
.name = "16",
.start = INT_DMA_LCD,
.flags = IORESOURCE_IRQ,
},
};
static void __iomem *dma_base;
static inline void dma_write(u32 val, int reg, int lch)
{
u8 stride;
u32 offset;
stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
offset = reg_map[reg] + (stride * lch);
__raw_writew(val, dma_base + offset);
if ((reg > CLNK_CTRL && reg < CCEN) ||
(reg > PCHD_ID && reg < CAPS_2)) {
u32 offset2 = reg_map[reg] + 2 + (stride * lch);
__raw_writew(val >> 16, dma_base + offset2);
}
}
static inline u32 dma_read(int reg, int lch)
{
u8 stride;
u32 offset, val;
stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
offset = reg_map[reg] + (stride * lch);
val = __raw_readw(dma_base + offset);
if ((reg > CLNK_CTRL && reg < CCEN) ||
(reg > PCHD_ID && reg < CAPS_2)) {
u16 upper;
u32 offset2 = reg_map[reg] + 2 + (stride * lch);
upper = __raw_readw(dma_base + offset2);
val |= (upper << 16);
}
return val;
}
static void omap1_clear_lch_regs(int lch)
{
int i = dma_common_ch_start;
for (; i <= dma_common_ch_end; i += 1)
dma_write(0, i, lch);
}
static void omap1_clear_dma(int lch)
{
u32 l;
l = dma_read(CCR, lch);
l &= ~OMAP_DMA_CCR_EN;
dma_write(l, CCR, lch);
/* Clear pending interrupts */
l = dma_read(CSR, lch);
}
static void omap1_show_dma_caps(void)
{
if (enable_1510_mode) {
printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
} else {
u16 w;
printk(KERN_INFO "OMAP DMA hardware version %d\n",
dma_read(HW_ID, 0));
printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
dma_read(CAPS_4, 0));
/* Disable OMAP 3.0/3.1 compatibility mode. */
w = dma_read(GSCR, 0);
w |= 1 << 3;
dma_write(w, GSCR, 0);
}
return;
}
static u32 configure_dma_errata(void)
{
/*
* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
* read before the DMA controller finished disabling the channel.
*/
if (!cpu_is_omap15xx())
SET_DMA_ERRATA(DMA_ERRATA_3_3);
return errata;
}
static int __init omap1_system_dma_init(void)
{
struct omap_system_dma_plat_info *p;
struct omap_dma_dev_attr *d;
struct platform_device *pdev;
int ret;
pdev = platform_device_alloc("omap_dma_system", 0);
if (!pdev) {
pr_err("%s: Unable to device alloc for dma\n",
__func__);
return -ENOMEM;
}
dma_base = ioremap(res[0].start, resource_size(&res[0]));
if (!dma_base) {
pr_err("%s: Unable to ioremap\n", __func__);
return -ENODEV;
}
ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
if (ret) {
dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
__func__, pdev->name, pdev->id);
goto exit_device_del;
}
p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
if (!p) {
dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
__func__, pdev->name);
ret = -ENOMEM;
goto exit_device_put;
}
d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
if (!d) {
dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
__func__, pdev->name);
ret = -ENOMEM;
goto exit_release_p;
}
d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
/* Valid attributes for omap1 plus processors */
if (cpu_is_omap15xx())
d->dev_caps = ENABLE_1510_MODE;
enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
d->dev_caps |= SRC_PORT;
d->dev_caps |= DST_PORT;
d->dev_caps |= SRC_INDEX;
d->dev_caps |= DST_INDEX;
d->dev_caps |= IS_BURST_ONLY4;
d->dev_caps |= CLEAR_CSR_ON_READ;
d->dev_caps |= IS_WORD_16;
d->chan = kzalloc(sizeof(struct omap_dma_lch) *
(d->lch_count), GFP_KERNEL);
if (!d->chan) {
dev_err(&pdev->dev, "%s: Memory allocation failed"
"for d->chan!!!\n", __func__);
goto exit_release_d;
}
if (cpu_is_omap15xx())
d->chan_count = 9;
else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
if (!(d->dev_caps & ENABLE_1510_MODE))
d->chan_count = 16;
else
d->chan_count = 9;
}
p->dma_attr = d;
p->show_dma_caps = omap1_show_dma_caps;
p->clear_lch_regs = omap1_clear_lch_regs;
p->clear_dma = omap1_clear_dma;
p->dma_write = dma_write;
p->dma_read = dma_read;
p->disable_irq_lch = NULL;
p->errata = configure_dma_errata();
ret = platform_device_add_data(pdev, p, sizeof(*p));
if (ret) {
dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
__func__, pdev->name, pdev->id);
goto exit_release_chan;
}
ret = platform_device_add(pdev);
if (ret) {
dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
__func__, pdev->name, pdev->id);
goto exit_release_chan;
}
dma_stride = OMAP1_DMA_STRIDE;
dma_common_ch_start = CPC;
dma_common_ch_end = COLOR;
return ret;
exit_release_chan:
kfree(d->chan);
exit_release_d:
kfree(d);
exit_release_p:
kfree(p);
exit_device_put:
platform_device_put(pdev);
exit_device_del:
platform_device_del(pdev);
return ret;
}
arch_initcall(omap1_system_dma_init);

4
arch/arm/mach-omap2/Kconfig
View File

@ -35,6 +35,8 @@ config ARCH_OMAP3
select CPU_V7
select USB_ARCH_HAS_EHCI
select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
select ARCH_HAS_OPP
select PM_OPP if PM
config ARCH_OMAP4
bool "TI OMAP4"
@ -44,6 +46,8 @@ config ARCH_OMAP4
select ARM_GIC
select PL310_ERRATA_588369
select ARM_ERRATA_720789
select ARCH_HAS_OPP
select PM_OPP if PM
comment "OMAP Core Type"
depends on ARCH_OMAP2

9
arch/arm/mach-omap2/Makefile
View File

@ -4,7 +4,7 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
common.o gpio.o
common.o gpio.o dma.o
omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o
hwmod-common = omap_hwmod.o \
@ -49,6 +49,13 @@ obj-$(CONFIG_ARCH_OMAP4) += mux44xx.o
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
# OPP table initialization
ifeq ($(CONFIG_PM_OPP),y)
obj-y += opp.o
obj-$(CONFIG_ARCH_OMAP3) += opp3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += opp4xxx_data.o
endif
# Power Management
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o

8
arch/arm/mach-omap2/board-devkit8000.c
View File

@ -118,27 +118,27 @@ static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0);
if (gpio_is_valid(dssdev->reset_gpio))
gpio_set_value(dssdev->reset_gpio, 1);
gpio_set_value_cansleep(dssdev->reset_gpio, 1);
return 0;
}
static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
{
if (gpio_is_valid(dssdev->reset_gpio))
gpio_set_value(dssdev->reset_gpio, 0);
gpio_set_value_cansleep(dssdev->reset_gpio, 0);
}
static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
{
if (gpio_is_valid(dssdev->reset_gpio))
gpio_set_value(dssdev->reset_gpio, 1);
gpio_set_value_cansleep(dssdev->reset_gpio, 1);
return 0;
}
static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
{
if (gpio_is_valid(dssdev->reset_gpio))
gpio_set_value(dssdev->reset_gpio, 0);
gpio_set_value_cansleep(dssdev->reset_gpio, 0);
}
static struct regulator_consumer_supply devkit8000_vmmc1_supply =

63
arch/arm/mach-omap2/board-h4.c
View File

@ -51,38 +51,37 @@
static unsigned int row_gpios[6] = { 88, 89, 124, 11, 6, 96 };
static unsigned int col_gpios[7] = { 90, 91, 100, 36, 12, 97, 98 };
static int h4_keymap[] = {
static const unsigned int h4_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_RIGHT),
KEY(0, 2, KEY_A),
KEY(0, 3, KEY_B),
KEY(0, 4, KEY_C),
KEY(1, 0, KEY_DOWN),
KEY(1, 0, KEY_RIGHT),
KEY(2, 0, KEY_A),
KEY(3, 0, KEY_B),
KEY(4, 0, KEY_C),
KEY(0, 1, KEY_DOWN),
KEY(1, 1, KEY_UP),
KEY(1, 2, KEY_E),
KEY(1, 3, KEY_F),
KEY(1, 4, KEY_G),
KEY(2, 0, KEY_ENTER),
KEY(2, 1, KEY_I),
KEY(2, 1, KEY_E),
KEY(3, 1, KEY_F),
KEY(4, 1, KEY_G),
KEY(0, 2, KEY_ENTER),
KEY(1, 2, KEY_I),
KEY(2, 2, KEY_J),
KEY(2, 3, KEY_K),
KEY(2, 4, KEY_3),
KEY(3, 0, KEY_M),
KEY(3, 1, KEY_N),
KEY(3, 2, KEY_O),
KEY(3, 2, KEY_K),
KEY(4, 2, KEY_3),
KEY(0, 3, KEY_M),
KEY(1, 3, KEY_N),
KEY(2, 3, KEY_O),
KEY(3, 3, KEY_P),
KEY(3, 4, KEY_Q),
KEY(4, 0, KEY_R),
KEY(4, 1, KEY_4),
KEY(4, 2, KEY_T),
KEY(4, 3, KEY_U),
KEY(4, 3, KEY_Q),
KEY(0, 4, KEY_R),
KEY(1, 4, KEY_4),
KEY(2, 4, KEY_T),
KEY(3, 4, KEY_U),
KEY(4, 4, KEY_ENTER),
KEY(5, 0, KEY_V),
KEY(5, 1, KEY_W),
KEY(5, 2, KEY_L),
KEY(5, 3, KEY_S),
KEY(5, 4, KEY_ENTER),
0
KEY(0, 5, KEY_V),
KEY(1, 5, KEY_W),
KEY(2, 5, KEY_L),
KEY(3, 5, KEY_S),
KEY(4, 5, KEY_ENTER),
};
static struct mtd_partition h4_partitions[] = {
@ -136,12 +135,16 @@ static struct platform_device h4_flash_device = {
.resource = &h4_flash_resource,
};
static const struct matrix_keymap_data h4_keymap_data = {
.keymap = h4_keymap,
.keymap_size = ARRAY_SIZE(h4_keymap),
};
static struct omap_kp_platform_data h4_kp_data = {
.rows = 6,
.cols = 7,
.keymap = h4_keymap,
.keymapsize = ARRAY_SIZE(h4_keymap),
.rep = 1,
.keymap_data = &h4_keymap_data,
.rep = true,
.row_gpios = row_gpios,
.col_gpios = col_gpios,
};

1
arch/arm/mach-omap2/board-omap4panda.c
View File

@ -142,6 +142,7 @@ static struct omap2_hsmmc_info mmc[] = {
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_wp = -EINVAL,
.gpio_cd = -EINVAL,
},
{} /* Terminator */
};

22
arch/arm/mach-omap2/board-rx51-peripherals.c
View File

@ -359,17 +359,12 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
REGULATOR_SUPPLY("DVDD", "2-0019"),
};
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
extern struct platform_device rx51_display_device;
#endif
static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
{
.supply = "vdds_sdi",
.dev = &rx51_display_device.dev,
},
#endif
REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
};
static struct regulator_consumer_supply rx51_vdac_supply[] = {
REGULATOR_SUPPLY("vdda_dac", "omapdss"),
};
static struct regulator_init_data rx51_vaux1 = {
@ -489,14 +484,17 @@ static struct regulator_init_data rx51_vsim = {
static struct regulator_init_data rx51_vdac = {
.constraints = {
.name = "VDAC",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = 1,
.consumer_supplies = rx51_vdac_supply,
};
static struct regulator_init_data rx51_vio = {

20
arch/arm/mach-omap2/board-rx51-video.c
View File

@ -24,9 +24,6 @@
#include "mux.h"
#define RX51_LCD_RESET_GPIO 90
/* REVISIT to verify with rx51.c at sound/soc/omap */
#define RX51_TVOUT_SEL_GPIO 40
#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
@ -41,17 +38,6 @@ static void rx51_lcd_disable(struct omap_dss_device *dssdev)
gpio_set_value(dssdev->reset_gpio, 0);
}
static int rx51_tvout_enable(struct omap_dss_device *dssdev)
{
gpio_set_value(dssdev->reset_gpio, 1);
return 0;
}
static void rx51_tvout_disable(struct omap_dss_device *dssdev)
{
gpio_set_value(dssdev->reset_gpio, 0);
}
static struct omap_dss_device rx51_lcd_device = {
.name = "lcd",
.driver_name = "panel-acx565akm",
@ -67,9 +53,6 @@ static struct omap_dss_device rx51_tv_device = {
.type = OMAP_DISPLAY_TYPE_VENC,
.driver_name = "venc",
.phy.venc.type = OMAP_DSS_VENC_TYPE_COMPOSITE,
.reset_gpio = RX51_TVOUT_SEL_GPIO,
.platform_enable = rx51_tvout_enable,
.platform_disable = rx51_tvout_disable,
};
static struct omap_dss_device *rx51_dss_devices[] = {
@ -112,9 +95,6 @@ static int __init rx51_video_init(void)
gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
/* REVISIT to verify with rx51.c at sound/soc/omap */
gpio_direction_output(RX51_TVOUT_SEL_GPIO, 1);
platform_add_devices(rx51_video_devices,
ARRAY_SIZE(rx51_video_devices));
return 0;

22
arch/arm/mach-omap2/control.c
View File

@ -239,9 +239,19 @@ void omap3_save_scratchpad_contents(void)
struct omap3_scratchpad_prcm_block prcm_block_contents;
struct omap3_scratchpad_sdrc_block sdrc_block_contents;
/* Populate the Scratchpad contents */
/*
* Populate the Scratchpad contents
*
* The "get_*restore_pointer" functions are used to provide a
* physical restore address where the ROM code jumps while waking
* up from MPU OFF/OSWR state.
* The restore pointer is stored into the scratchpad.
*/
scratchpad_contents.boot_config_ptr = 0x0;
if (omap_rev() != OMAP3430_REV_ES3_0 &&
if (cpu_is_omap3630())
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_omap3630_restore_pointer());
else if (omap_rev() != OMAP3430_REV_ES3_0 &&
omap_rev() != OMAP3430_REV_ES3_1)
scratchpad_contents.public_restore_ptr =
virt_to_phys(get_restore_pointer());
@ -474,4 +484,12 @@ void omap3_control_restore_context(void)
omap_ctrl_writel(control_context.csi, OMAP343X_CONTROL_CSI);
return;
}
void omap3630_ctrl_disable_rta(void)
{
if (!cpu_is_omap3630())
return;
omap_ctrl_writel(OMAP36XX_RTA_DISABLE, OMAP36XX_CONTROL_MEM_RTA_CTRL);
}
#endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */

11
arch/arm/mach-omap2/control.h
View File

@ -204,6 +204,10 @@
#define OMAP343X_CONTROL_WKUP_DEBOBS3 (OMAP343X_CONTROL_GENERAL_WKUP + 0x014)
#define OMAP343X_CONTROL_WKUP_DEBOBS4 (OMAP343X_CONTROL_GENERAL_WKUP + 0x018)
/* 36xx-only RTA - Retention till Accesss control registers and bits */
#define OMAP36XX_CONTROL_MEM_RTA_CTRL 0x40C
#define OMAP36XX_RTA_DISABLE 0x0
/* 34xx D2D idle-related pins, handled by PM core */
#define OMAP3_PADCONF_SAD2D_MSTANDBY 0x250
#define OMAP3_PADCONF_SAD2D_IDLEACK 0x254
@ -270,6 +274,8 @@
#define OMAP343X_SCRATCHPAD_ROM (OMAP343X_CTRL_BASE + 0x860)
#define OMAP343X_SCRATCHPAD (OMAP343X_CTRL_BASE + 0x910)
#define OMAP343X_SCRATCHPAD_ROM_OFFSET 0x19C
#define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
OMAP343X_SCRATCHPAD + reg)
/* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
#define AM35XX_USBOTG_VBUSP_CLK_SHIFT 0
@ -309,7 +315,7 @@
#define FEAT_SGX_NONE 2
#define OMAP3_IVA_SHIFT 12
#define OMAP3_IVA_MASK (1 << OMAP3_SGX_SHIFT)
#define OMAP3_IVA_MASK (1 << OMAP3_IVA_SHIFT)
#define FEAT_IVA 0
#define FEAT_IVA_NONE 1
@ -347,10 +353,11 @@ extern void omap3_save_scratchpad_contents(void);
extern void omap3_clear_scratchpad_contents(void);
extern u32 *get_restore_pointer(void);
extern u32 *get_es3_restore_pointer(void);
extern u32 *get_omap3630_restore_pointer(void);
extern u32 omap3_arm_context[128];
extern void omap3_control_save_context(void);
extern void omap3_control_restore_context(void);
extern void omap3630_ctrl_disable_rta(void);
#else
#define omap_ctrl_base_get() 0
#define omap_ctrl_readb(x) 0

36
arch/arm/mach-omap2/cpuidle34xx.c
View File

@ -293,25 +293,26 @@ select_state:
DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
/**
* omap3_cpuidle_update_states - Update the cpuidle states.
* omap3_cpuidle_update_states() - Update the cpuidle states
* @mpu_deepest_state: Enable states upto and including this for mpu domain
* @core_deepest_state: Enable states upto and including this for core domain
*
* Currently, this function toggles the validity of idle states based upon
* the flag 'enable_off_mode'. When the flag is set all states are valid.
* Else, states leading to OFF state set to be invalid.
* This goes through the list of states available and enables and disables the
* validity of C states based on deepest state that can be achieved for the
* variable domain
*/
void omap3_cpuidle_update_states(void)
void omap3_cpuidle_update_states(u32 mpu_deepest_state, u32 core_deepest_state)
{
int i;
for (i = OMAP3_STATE_C1; i < OMAP3_MAX_STATES; i++) {
struct omap3_processor_cx *cx = &omap3_power_states[i];
if (enable_off_mode) {
if ((cx->mpu_state >= mpu_deepest_state) &&
(cx->core_state >= core_deepest_state)) {
cx->valid = 1;
} else {
if ((cx->mpu_state == PWRDM_POWER_OFF) ||
(cx->core_state == PWRDM_POWER_OFF))
cx->valid = 0;
cx->valid = 0;
}
}
}
@ -452,6 +453,18 @@ void omap_init_power_states(void)
omap3_power_states[OMAP3_STATE_C7].core_state = PWRDM_POWER_OFF;
omap3_power_states[OMAP3_STATE_C7].flags = CPUIDLE_FLAG_TIME_VALID |
CPUIDLE_FLAG_CHECK_BM;
/*
* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
* enable OFF mode in a stable form for previous revisions.
* we disable C7 state as a result.
*/
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
omap3_power_states[OMAP3_STATE_C7].valid = 0;
cpuidle_params_table[OMAP3_STATE_C7].valid = 0;
WARN_ONCE(1, "%s: core off state C7 disabled due to i583\n",
__func__);
}
}
struct cpuidle_driver omap3_idle_driver = {
@ -504,7 +517,10 @@ int __init omap3_idle_init(void)
return -EINVAL;
dev->state_count = count;
omap3_cpuidle_update_states();
if (enable_off_mode)
omap3_cpuidle_update_states(PWRDM_POWER_OFF, PWRDM_POWER_OFF);
else
omap3_cpuidle_update_states(PWRDM_POWER_RET, PWRDM_POWER_RET);
if (cpuidle_register_device(dev)) {
printk(KERN_ERR "%s: CPUidle register device failed\n",

297
arch/arm/mach-omap2/dma.c Normal file
View File

@ -0,0 +1,297 @@
/*
* OMAP2+ DMA driver
*
* Copyright (C) 2003 - 2008 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
* Graphics DMA and LCD DMA graphics tranformations
* by Imre Deak <imre.deak@nokia.com>
* OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
*
* Copyright (C) 2009 Texas Instruments
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Converted DMA library into platform driver
* - G, Manjunath Kondaiah <manjugk@ti.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
#include <plat/dma.h>
#define OMAP2_DMA_STRIDE 0x60
static u32 errata;
static u8 dma_stride;
static struct omap_dma_dev_attr *d;
static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
static u16 reg_map[] = {
[REVISION] = 0x00,
[GCR] = 0x78,
[IRQSTATUS_L0] = 0x08,
[IRQSTATUS_L1] = 0x0c,
[IRQSTATUS_L2] = 0x10,
[IRQSTATUS_L3] = 0x14,
[IRQENABLE_L0] = 0x18,
[IRQENABLE_L1] = 0x1c,
[IRQENABLE_L2] = 0x20,
[IRQENABLE_L3] = 0x24,
[SYSSTATUS] = 0x28,
[OCP_SYSCONFIG] = 0x2c,
[CAPS_0] = 0x64,
[CAPS_2] = 0x6c,
[CAPS_3] = 0x70,
[CAPS_4] = 0x74,
/* Common register offsets */
[CCR] = 0x80,
[CLNK_CTRL] = 0x84,
[CICR] = 0x88,
[CSR] = 0x8c,
[CSDP] = 0x90,
[CEN] = 0x94,
[CFN] = 0x98,
[CSEI] = 0xa4,
[CSFI] = 0xa8,
[CDEI] = 0xac,
[CDFI] = 0xb0,
[CSAC] = 0xb4,
[CDAC] = 0xb8,
/* Channel specific register offsets */
[CSSA] = 0x9c,
[CDSA] = 0xa0,
[CCEN] = 0xbc,
[CCFN] = 0xc0,
[COLOR] = 0xc4,
/* OMAP4 specific registers */
[CDP] = 0xd0,
[CNDP] = 0xd4,
[CCDN] = 0xd8,
};
static struct omap_device_pm_latency omap2_dma_latency[] = {
{
.deactivate_func = omap_device_idle_hwmods,
.activate_func = omap_device_enable_hwmods,
.flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
},
};
static void __iomem *dma_base;
static inline void dma_write(u32 val, int reg, int lch)
{
u8 stride;
u32 offset;
stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
offset = reg_map[reg] + (stride * lch);
__raw_writel(val, dma_base + offset);
}
static inline u32 dma_read(int reg, int lch)
{
u8 stride;
u32 offset, val;
stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
offset = reg_map[reg] + (stride * lch);
val = __raw_readl(dma_base + offset);
return val;
}
static inline void omap2_disable_irq_lch(int lch)
{
u32 val;
val = dma_read(IRQENABLE_L0, lch);
val &= ~(1 << lch);
dma_write(val, IRQENABLE_L0, lch);
}
static void omap2_clear_dma(int lch)
{
int i = dma_common_ch_start;
for (; i <= dma_common_ch_end; i += 1)
dma_write(0, i, lch);
}
static void omap2_show_dma_caps(void)
{
u8 revision = dma_read(REVISION, 0) & 0xff;
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
revision >> 4, revision & 0xf);
return;
}
static u32 configure_dma_errata(void)
{
/*
* Errata applicable for OMAP2430ES1.0 and all omap2420
*
* I.
* Erratum ID: Not Available
* Inter Frame DMA buffering issue DMA will wrongly
* buffer elements if packing and bursting is enabled. This might
* result in data gets stalled in FIFO at the end of the block.
* Workaround: DMA channels must have BUFFERING_DISABLED bit set to
* guarantee no data will stay in the DMA FIFO in case inter frame
* buffering occurs
*
* II.
* Erratum ID: Not Available
* DMA may hang when several channels are used in parallel
* In the following configuration, DMA channel hanging can occur:
* a. Channel i, hardware synchronized, is enabled
* b. Another channel (Channel x), software synchronized, is enabled.
* c. Channel i is disabled before end of transfer
* d. Channel i is reenabled.
* e. Steps 1 to 4 are repeated a certain number of times.
* f. A third channel (Channel y), software synchronized, is enabled.
* Channel x and Channel y may hang immediately after step 'f'.
* Workaround:
* For any channel used - make sure NextLCH_ID is set to the value j.
*/
if (cpu_is_omap2420() || (cpu_is_omap2430() &&
(omap_type() == OMAP2430_REV_ES1_0))) {
SET_DMA_ERRATA(DMA_ERRATA_IFRAME_BUFFERING);
SET_DMA_ERRATA(DMA_ERRATA_PARALLEL_CHANNELS);
}
/*
* Erratum ID: i378: OMAP2+: sDMA Channel is not disabled
* after a transaction error.
* Workaround: SW should explicitely disable the channel.
*/
if (cpu_class_is_omap2())
SET_DMA_ERRATA(DMA_ERRATA_i378);
/*
* Erratum ID: i541: sDMA FIFO draining does not finish
* If sDMA channel is disabled on the fly, sDMA enters standby even
* through FIFO Drain is still in progress
* Workaround: Put sDMA in NoStandby more before a logical channel is
* disabled, then put it back to SmartStandby right after the channel
* finishes FIFO draining.
*/
if (cpu_is_omap34xx())
SET_DMA_ERRATA(DMA_ERRATA_i541);
/*
* Erratum ID: i88 : Special programming model needed to disable DMA
* before end of block.
* Workaround: software must ensure that the DMA is configured in No
* Standby mode(DMAx_OCP_SYSCONFIG.MIDLEMODE = "01")
*/
if (omap_type() == OMAP3430_REV_ES1_0)
SET_DMA_ERRATA(DMA_ERRATA_i88);
/*
* Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
* read before the DMA controller finished disabling the channel.
*/
SET_DMA_ERRATA(DMA_ERRATA_3_3);
/*
* Erratum ID: Not Available
* A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
* after secure sram context save and restore.
* Work around: Hence we need to manually clear those IRQs to avoid
* spurious interrupts. This affects only secure devices.
*/
if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
SET_DMA_ERRATA(DMA_ROMCODE_BUG);
return errata;
}
/* One time initializations */
static int __init omap2_system_dma_init_dev(struct omap_hwmod *oh, void *unused)
{
struct omap_device *od;
struct omap_system_dma_plat_info *p;
struct resource *mem;
char *name = "omap_dma_system";
dma_stride = OMAP2_DMA_STRIDE;
dma_common_ch_start = CSDP;
if (cpu_is_omap3630() || cpu_is_omap4430())
dma_common_ch_end = CCDN;
else
dma_common_ch_end = CCFN;
p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
if (!p) {
pr_err("%s: Unable to allocate pdata for %s:%s\n",
__func__, name, oh->name);
return -ENOMEM;
}
p->dma_attr = (struct omap_dma_dev_attr *)oh->dev_attr;
p->disable_irq_lch = omap2_disable_irq_lch;
p->show_dma_caps = omap2_show_dma_caps;
p->clear_dma = omap2_clear_dma;
p->dma_write = dma_write;
p->dma_read = dma_read;
p->clear_lch_regs = NULL;
p->errata = configure_dma_errata();
od = omap_device_build(name, 0, oh, p, sizeof(*p),
omap2_dma_latency, ARRAY_SIZE(omap2_dma_latency), 0);
kfree(p);
if (IS_ERR(od)) {
pr_err("%s: Cant build omap_device for %s:%s.\n",
__func__, name, oh->name);
return IS_ERR(od);
}
mem = platform_get_resource(&od->pdev, IORESOURCE_MEM, 0);
if (!mem) {
dev_err(&od->pdev.dev, "%s: no mem resource\n", __func__);
return -EINVAL;
}
dma_base = ioremap(mem->start, resource_size(mem));
if (!dma_base) {
dev_err(&od->pdev.dev, "%s: ioremap fail\n", __func__);
return -ENOMEM;
}
d = oh->dev_attr;
d->chan = kzalloc(sizeof(struct omap_dma_lch) *
(d->lch_count), GFP_KERNEL);
if (!d->chan) {
dev_err(&od->pdev.dev, "%s: kzalloc fail\n", __func__);
return -ENOMEM;
}
return 0;
}
static int __init omap2_system_dma_init(void)
{
return omap_hwmod_for_each_by_class("dma",
omap2_system_dma_init_dev, NULL);
}
arch_initcall(omap2_system_dma_init);

3
arch/arm/mach-omap2/io.c
View File

@ -347,8 +347,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
else if (cpu_is_omap44xx())
omap44xx_hwmod_init();
/* The OPP tables have to be registered before a clk init */
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
omap_pm_if_early_init();
if (cpu_is_omap2420())
omap2420_clk_init();

86
arch/arm/mach-omap2/omap_hwmod_2420_data.c
View File

@ -42,6 +42,7 @@ static struct omap_hwmod omap2420_gpio1_hwmod;
static struct omap_hwmod omap2420_gpio2_hwmod;
static struct omap_hwmod omap2420_gpio3_hwmod;
static struct omap_hwmod omap2420_gpio4_hwmod;
static struct omap_hwmod omap2420_dma_system_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@ -779,6 +780,88 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* system dma */
static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
SYSC_HAS_AUTOIDLE),
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2420_dma_hwmod_class = {
.name = "dma",
.sysc = &omap2420_dma_sysc,
};
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32,
.lch_count = 32,
};
static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
};
static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x4a0560ff,
.flags = ADDR_TYPE_RT
},
};
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
.master = &omap2420_dma_system_hwmod,
.slave = &omap2420_l3_main_hwmod,
.clk = "core_l3_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system master ports */
static struct omap_hwmod_ocp_if *omap2420_dma_system_masters[] = {
&omap2420_dma_system__l3,
};
/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dma_system_hwmod,
.clk = "sdma_ick",
.addr = omap2420_dma_system_addrs,
.addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system slave ports */
static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
&omap2420_l4_core__dma_system,
};
static struct omap_hwmod omap2420_dma_system_hwmod = {
.name = "dma",
.class = &omap2420_dma_hwmod_class,
.mpu_irqs = omap2420_dma_system_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
.main_clk = "core_l3_ck",
.slaves = omap2420_dma_system_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
.masters = omap2420_dma_system_masters,
.masters_cnt = ARRAY_SIZE(omap2420_dma_system_masters),
.dev_attr = &dma_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
.flags = HWMOD_NO_IDLEST,
};
static __initdata struct omap_hwmod *omap2420_hwmods[] = {
&omap2420_l3_main_hwmod,
&omap2420_l4_core_hwmod,
@ -797,6 +880,9 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
&omap2420_gpio2_hwmod,
&omap2420_gpio3_hwmod,
&omap2420_gpio4_hwmod,
/* dma_system class*/
&omap2420_dma_system_hwmod,
NULL,
};

86
arch/arm/mach-omap2/omap_hwmod_2430_data.c
View File

@ -43,6 +43,7 @@ static struct omap_hwmod omap2430_gpio2_hwmod;
static struct omap_hwmod omap2430_gpio3_hwmod;
static struct omap_hwmod omap2430_gpio4_hwmod;
static struct omap_hwmod omap2430_gpio5_hwmod;
static struct omap_hwmod omap2430_dma_system_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@ -838,6 +839,88 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* dma_system */
static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
SYSC_HAS_AUTOIDLE),
.idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap2430_dma_hwmod_class = {
.name = "dma",
.sysc = &omap2430_dma_sysc,
};
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
.lch_count = 32,
};
static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
};
static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x4a0560ff,
.flags = ADDR_TYPE_RT
},
};
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
.master = &omap2430_dma_system_hwmod,
.slave = &omap2430_l3_main_hwmod,
.clk = "core_l3_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system master ports */
static struct omap_hwmod_ocp_if *omap2430_dma_system_masters[] = {
&omap2430_dma_system__l3,
};
/* l4_core -> dma_system */
static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dma_system_hwmod,
.clk = "sdma_ick",
.addr = omap2430_dma_system_addrs,
.addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system slave ports */
static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
&omap2430_l4_core__dma_system,
};
static struct omap_hwmod omap2430_dma_system_hwmod = {
.name = "dma",
.class = &omap2430_dma_hwmod_class,
.mpu_irqs = omap2430_dma_system_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
.main_clk = "core_l3_ck",
.slaves = omap2430_dma_system_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
.masters = omap2430_dma_system_masters,
.masters_cnt = ARRAY_SIZE(omap2430_dma_system_masters),
.dev_attr = &dma_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
.flags = HWMOD_NO_IDLEST,
};
static __initdata struct omap_hwmod *omap2430_hwmods[] = {
&omap2430_l3_main_hwmod,
&omap2430_l4_core_hwmod,
@ -857,6 +940,9 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
&omap2430_gpio3_hwmod,
&omap2430_gpio4_hwmod,
&omap2430_gpio5_hwmod,
/* dma_system class*/
&omap2430_dma_system_hwmod,
NULL,
};

97
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -52,6 +52,8 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod;
static struct omap_hwmod omap3xxx_gpio5_hwmod;
static struct omap_hwmod omap3xxx_gpio6_hwmod;
static struct omap_hwmod omap3xxx_dma_system_hwmod;
/* L3 -> L4_CORE interface */
static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
.master = &omap3xxx_l3_main_hwmod,
@ -1090,6 +1092,98 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap3xxx_dma_system__l3 = {
.master = &omap3xxx_dma_system_hwmod,
.slave = &omap3xxx_l3_main_hwmod,
.clk = "core_l3_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
.lch_count = 32,
};
static struct omap_hwmod_class_sysconfig omap3xxx_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_MIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
.name = "dma",
.sysc = &omap3xxx_dma_sysc,
};
/* dma_system */
static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
{ .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
{ .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
{ .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
{ .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
};
static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x4a0560ff,
.flags = ADDR_TYPE_RT
},
};
/* dma_system master ports */
static struct omap_hwmod_ocp_if *omap3xxx_dma_system_masters[] = {
&omap3xxx_dma_system__l3,
};
/* l4_cfg -> dma_system */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dma_system_hwmod,
.clk = "core_l4_ick",
.addr = omap3xxx_dma_system_addrs,
.addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system slave ports */
static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
&omap3xxx_l4_core__dma_system,
};
static struct omap_hwmod omap3xxx_dma_system_hwmod = {
.name = "dma",
.class = &omap3xxx_dma_hwmod_class,
.mpu_irqs = omap3xxx_dma_system_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
.main_clk = "core_l3_ick",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.prcm_reg_id = 1,
.module_bit = OMAP3430_ST_SDMA_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
},
},
.slaves = omap3xxx_dma_system_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_dma_system_slaves),
.masters = omap3xxx_dma_system_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_dma_system_masters),
.dev_attr = &dma_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
.flags = HWMOD_NO_IDLEST,
};
static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_l3_main_hwmod,
&omap3xxx_l4_core_hwmod,
@ -1113,6 +1207,9 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
&omap3xxx_gpio4_hwmod,
&omap3xxx_gpio5_hwmod,
&omap3xxx_gpio6_hwmod,
/* dma_system class*/
&omap3xxx_dma_system_hwmod,
NULL,
};

102
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
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@ -23,6 +23,7 @@
#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
#include <plat/gpio.h>
#include <plat/dma.h>
#include "omap_hwmod_common_data.h"
@ -36,6 +37,7 @@
#define OMAP44XX_DMA_REQ_START 1
/* Backward references (IPs with Bus Master capability) */
static struct omap_hwmod omap44xx_dma_system_hwmod;
static struct omap_hwmod omap44xx_dmm_hwmod;
static struct omap_hwmod omap44xx_emif_fw_hwmod;
static struct omap_hwmod omap44xx_l3_instr_hwmod;
@ -216,6 +218,14 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
.master = &omap44xx_dma_system_hwmod,
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_cfg -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
.master = &omap44xx_l4_cfg_hwmod,
@ -226,6 +236,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
/* l3_main_2 slave ports */
static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
&omap44xx_dma_system__l3_main_2,
&omap44xx_l3_main_1__l3_main_2,
&omap44xx_l4_cfg__l3_main_2,
};
@ -1376,6 +1387,93 @@ static struct omap_hwmod omap44xx_gpio6_hwmod = {
.slaves_cnt = ARRAY_SIZE(omap44xx_gpio6_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
/*
* 'dma' class
* dma controller for data exchange between memory to memory (i.e. internal or
* external memory) and gp peripherals to memory or memory to gp peripherals
*/
static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
.rev_offs = 0x0000,
.sysc_offs = 0x002c,
.syss_offs = 0x0028,
.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
.sysc_fields = &omap_hwmod_sysc_type1,
};
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
.lch_count = 32,
};
static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
.name = "dma",
.sysc = &omap44xx_dma_sysc,
};
/* dma_system */
static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
{ .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START },
{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
};
/* dma_system master ports */
static struct omap_hwmod_ocp_if *omap44xx_dma_system_masters[] = {
&omap44xx_dma_system__l3_main_2,
};
static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
{
.pa_start = 0x4a056000,
.pa_end = 0x4a0560ff,
.flags = ADDR_TYPE_RT
},
};
/* l4_cfg -> dma_system */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
.master = &omap44xx_l4_cfg_hwmod,
.slave = &omap44xx_dma_system_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dma_system_addrs,
.addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* dma_system slave ports */
static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
&omap44xx_l4_cfg__dma_system,
};
static struct omap_hwmod omap44xx_dma_system_hwmod = {
.name = "dma_system",
.class = &omap44xx_dma_hwmod_class,
.mpu_irqs = omap44xx_dma_system_irqs,
.mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
.main_clk = "l3_div_ck",
.prcm = {
.omap4 = {
.clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
},
},
.slaves = omap44xx_dma_system_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dma_system_slaves),
.masters = omap44xx_dma_system_masters,
.masters_cnt = ARRAY_SIZE(omap44xx_dma_system_masters),
.dev_attr = &dma_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
/* dmm class */
&omap44xx_dmm_hwmod,
@ -1391,6 +1489,10 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
&omap44xx_l4_cfg_hwmod,
&omap44xx_l4_per_hwmod,
&omap44xx_l4_wkup_hwmod,
/* dma class */
&omap44xx_dma_system_hwmod,
/* i2c class */
&omap44xx_i2c1_hwmod,
&omap44xx_i2c2_hwmod,

72
arch/arm/mach-omap2/omap_opp_data.h Normal file
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@ -0,0 +1,72 @@
/*
* OMAP SoC specific OPP Data helpers
*
* Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Copyright (C) 2010 Nokia Corporation.
* Eduardo Valentin
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
#define __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H
#include <plat/omap_hwmod.h>
/*
* *BIG FAT WARNING*:
* USE the following ONLY in opp data initialization common to an SoC.
* DO NOT USE these in board files/pm core etc.
*/
/**
* struct omap_opp_def - OMAP OPP Definition
* @hwmod_name: Name of the hwmod for this domain
* @freq: Frequency in hertz corresponding to this OPP
* @u_volt: Nominal voltage in microvolts corresponding to this OPP
* @default_available: True/false - is this OPP available by default
*
* OMAP SOCs have a standard set of tuples consisting of frequency and voltage
* pairs that the device will support per voltage domain. This is called
* Operating Points or OPP. The actual definitions of OMAP Operating Points
* varies over silicon within the same family of devices. For a specific
* domain, you can have a set of {frequency, voltage} pairs and this is denoted
* by an array of omap_opp_def. As the kernel boots and more information is
* available, a set of these are activated based on the precise nature of
* device the kernel boots up on. It is interesting to remember that each IP
* which belongs to a voltage domain may define their own set of OPPs on top
* of this - but this is handled by the appropriate driver.
*/
struct omap_opp_def {
char *hwmod_name;
unsigned long freq;
unsigned long u_volt;
bool default_available;
};
/*
* Initialization wrapper used to define an OPP for OMAP variants.
*/
#define OPP_INITIALIZER(_hwmod_name, _enabled, _freq, _uv) \
{ \
.hwmod_name = _hwmod_name, \
.default_available = _enabled, \
.freq = _freq, \
.u_volt = _uv, \
}
/* Use this to initialize the default table */
extern int __init omap_init_opp_table(struct omap_opp_def *opp_def,
u32 opp_def_size);
#endif /* __ARCH_ARM_MACH_OMAP2_OMAP_OPP_DATA_H */

93
arch/arm/mach-omap2/opp.c Normal file
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@ -0,0 +1,93 @@
/*
* OMAP SoC specific OPP wrapper function
*
* Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Copyright (C) 2010 Nokia Corporation.
* Eduardo Valentin
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <linux/opp.h>
#include <plat/omap_device.h>
#include "omap_opp_data.h"
/* Temp variable to allow multiple calls */
static u8 __initdata omap_table_init;
/**
* omap_init_opp_table() - Initialize opp table as per the CPU type
* @opp_def: opp default list for this silicon
* @opp_def_size: number of opp entries for this silicon
*
* Register the initial OPP table with the OPP library based on the CPU
* type. This is meant to be used only by SoC specific registration.
*/
int __init omap_init_opp_table(struct omap_opp_def *opp_def,
u32 opp_def_size)
{
int i, r;
if (!opp_def || !opp_def_size) {
pr_err("%s: invalid params!\n", __func__);
return -EINVAL;
}
/*
* Initialize only if not already initialized even if the previous
* call failed, because, no reason we'd succeed again.
*/
if (omap_table_init)
return -EEXIST;
omap_table_init = 1;
/* Lets now register with OPP library */
for (i = 0; i < opp_def_size; i++) {
struct omap_hwmod *oh;
struct device *dev;
if (!opp_def->hwmod_name) {
pr_err("%s: NULL name of omap_hwmod, failing [%d].\n",
__func__, i);
return -EINVAL;
}
oh = omap_hwmod_lookup(opp_def->hwmod_name);
if (!oh || !oh->od) {
pr_warn("%s: no hwmod or odev for %s, [%d] "
"cannot add OPPs.\n", __func__,
opp_def->hwmod_name, i);
return -EINVAL;
}
dev = &oh->od->pdev.dev;
r = opp_add(dev, opp_def->freq, opp_def->u_volt);
if (r) {
dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
"result=%d\n",
__func__, opp_def->freq,
opp_def->hwmod_name, i, r);
} else {
if (!opp_def->default_available)
r = opp_disable(dev, opp_def->freq);
if (r)
dev_err(dev, "%s: disable %ld failed for %s "
"[%d] result=%d\n",
__func__, opp_def->freq,
opp_def->hwmod_name, i, r);
}
opp_def++;
}
return 0;
}

107
arch/arm/mach-omap2/opp3xxx_data.c Normal file
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@ -0,0 +1,107 @@
/*
* OMAP3 OPP table definitions.
*
* Copyright (C) 2009-2010 Texas Instruments Incorporated - http://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Copyright (C) 2010 Nokia Corporation.
* Eduardo Valentin
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <plat/cpu.h>
#include "omap_opp_data.h"
static struct omap_opp_def __initdata omap34xx_opp_def_list[] = {
/* MPU OPP1 */
OPP_INITIALIZER("mpu", true, 125000000, 975000),
/* MPU OPP2 */
OPP_INITIALIZER("mpu", true, 250000000, 1075000),
/* MPU OPP3 */
OPP_INITIALIZER("mpu", true, 500000000, 1200000),
/* MPU OPP4 */
OPP_INITIALIZER("mpu", true, 550000000, 1270000),
/* MPU OPP5 */
OPP_INITIALIZER("mpu", true, 600000000, 1350000),
/*
* L3 OPP1 - 41.5 MHz is disabled because: The voltage for that OPP is
* almost the same than the one at 83MHz thus providing very little
* gain for the power point of view. In term of energy it will even
* increase the consumption due to the very negative performance
* impact that frequency will do to the MPU and the whole system in
* general.
*/
OPP_INITIALIZER("l3_main", false, 41500000, 975000),
/* L3 OPP2 */
OPP_INITIALIZER("l3_main", true, 83000000, 1050000),
/* L3 OPP3 */
OPP_INITIALIZER("l3_main", true, 166000000, 1150000),
/* DSP OPP1 */
OPP_INITIALIZER("iva", true, 90000000, 975000),
/* DSP OPP2 */
OPP_INITIALIZER("iva", true, 180000000, 1075000),
/* DSP OPP3 */
OPP_INITIALIZER("iva", true, 360000000, 1200000),
/* DSP OPP4 */
OPP_INITIALIZER("iva", true, 400000000, 1270000),
/* DSP OPP5 */
OPP_INITIALIZER("iva", true, 430000000, 1350000),
};
static struct omap_opp_def __initdata omap36xx_opp_def_list[] = {
/* MPU OPP1 - OPP50 */
OPP_INITIALIZER("mpu", true, 300000000, 1012500),
/* MPU OPP2 - OPP100 */
OPP_INITIALIZER("mpu", true, 600000000, 1200000),
/* MPU OPP3 - OPP-Turbo */
OPP_INITIALIZER("mpu", false, 800000000, 1325000),
/* MPU OPP4 - OPP-SB */
OPP_INITIALIZER("mpu", false, 1000000000, 1375000),
/* L3 OPP1 - OPP50 */
OPP_INITIALIZER("l3_main", true, 100000000, 1000000),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
OPP_INITIALIZER("l3_main", true, 200000000, 1200000),
/* DSP OPP1 - OPP50 */
OPP_INITIALIZER("iva", true, 260000000, 1012500),
/* DSP OPP2 - OPP100 */
OPP_INITIALIZER("iva", true, 520000000, 1200000),
/* DSP OPP3 - OPP-Turbo */
OPP_INITIALIZER("iva", false, 660000000, 1325000),
/* DSP OPP4 - OPP-SB */
OPP_INITIALIZER("iva", false, 800000000, 1375000),
};
/**
* omap3_opp_init() - initialize omap3 opp table
*/
static int __init omap3_opp_init(void)
{
int r = -ENODEV;
if (!cpu_is_omap34xx())
return r;
if (cpu_is_omap3630())
r = omap_init_opp_table(omap36xx_opp_def_list,
ARRAY_SIZE(omap36xx_opp_def_list));
else
r = omap_init_opp_table(omap34xx_opp_def_list,
ARRAY_SIZE(omap34xx_opp_def_list));
return r;
}
device_initcall(omap3_opp_init);

57
arch/arm/mach-omap2/opp4xxx_data.c Normal file
View File

@ -0,0 +1,57 @@
/*
* OMAP4 OPP table definitions.
*
* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
* Nishanth Menon
* Kevin Hilman
* Thara Gopinath
* Copyright (C) 2010 Nokia Corporation.
* Eduardo Valentin
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/module.h>
#include <plat/cpu.h>
#include "omap_opp_data.h"
static struct omap_opp_def __initdata omap44xx_opp_def_list[] = {
/* MPU OPP1 - OPP50 */
OPP_INITIALIZER("mpu", true, 300000000, 1100000),
/* MPU OPP2 - OPP100 */
OPP_INITIALIZER("mpu", true, 600000000, 1200000),
/* MPU OPP3 - OPP-Turbo */
OPP_INITIALIZER("mpu", false, 800000000, 1260000),
/* MPU OPP4 - OPP-SB */
OPP_INITIALIZER("mpu", false, 1008000000, 1350000),
/* L3 OPP1 - OPP50 */
OPP_INITIALIZER("l3_main_1", true, 100000000, 930000),
/* L3 OPP2 - OPP100, OPP-Turbo, OPP-SB */
OPP_INITIALIZER("l3_main_1", true, 200000000, 1100000),
/* TODO: add IVA, DSP, aess, fdif, gpu */
};
/**
* omap4_opp_init() - initialize omap4 opp table
*/
static int __init omap4_opp_init(void)
{
int r = -ENODEV;
if (!cpu_is_omap44xx())
return r;
r = omap_init_opp_table(omap44xx_opp_def_list,
ARRAY_SIZE(omap44xx_opp_def_list));
return r;
}
device_initcall(omap4_opp_init);

2
arch/arm/mach-omap2/pm.c
View File

@ -143,5 +143,5 @@ static int __init omap2_common_pm_init(void)
return 0;
}
device_initcall(omap2_common_pm_init);
postcore_initcall(omap2_common_pm_init);

29
arch/arm/mach-omap2/pm.h
View File

@ -20,6 +20,20 @@ extern int omap3_can_sleep(void);
extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
extern int omap3_idle_init(void);
#if defined(CONFIG_PM_OPP)
extern int omap3_opp_init(void);
extern int omap4_opp_init(void);
#else
static inline int omap3_opp_init(void)
{
return -EINVAL;
}
static inline int omap4_opp_init(void)
{
return -EINVAL;
}
#endif
struct cpuidle_params {
u8 valid;
u32 sleep_latency;
@ -58,7 +72,7 @@ extern u32 sleep_while_idle;
#endif
#if defined(CONFIG_CPU_IDLE)
extern void omap3_cpuidle_update_states(void);
extern void omap3_cpuidle_update_states(u32, u32);
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
@ -80,9 +94,20 @@ extern void save_secure_ram_context(u32 *addr);
extern void omap3_save_scratchpad_contents(void);
extern unsigned int omap24xx_idle_loop_suspend_sz;
extern unsigned int omap34xx_suspend_sz;
extern unsigned int save_secure_ram_context_sz;
extern unsigned int omap24xx_cpu_suspend_sz;
extern unsigned int omap34xx_cpu_suspend_sz;
#define PM_RTA_ERRATUM_i608 (1 << 0)
#define PM_SDRC_WAKEUP_ERRATUM_i583 (1 << 1)
#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
extern u16 pm34xx_errata;
#define IS_PM34XX_ERRATUM(id) (pm34xx_errata & (id))
extern void enable_omap3630_toggle_l2_on_restore(void);
#else
#define IS_PM34XX_ERRATUM(id) 0
static inline void enable_omap3630_toggle_l2_on_restore(void) { }
#endif /* defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) */
#endif

16
arch/arm/mach-omap2/pm24xx.c
View File

@ -301,14 +301,8 @@ out:
static int omap2_pm_begin(suspend_state_t state)
{
suspend_state = state;
return 0;
}
static int omap2_pm_prepare(void)
{
/* We cannot sleep in idle until we have resumed */
disable_hlt();
suspend_state = state;
return 0;
}
@ -349,21 +343,15 @@ static int omap2_pm_enter(suspend_state_t state)
return ret;
}
static void omap2_pm_finish(void)
{
enable_hlt();
}
static void omap2_pm_end(void)
{
suspend_state = PM_SUSPEND_ON;
enable_hlt();
}
static struct platform_suspend_ops omap_pm_ops = {
.begin = omap2_pm_begin,
.prepare = omap2_pm_prepare,
.enter = omap2_pm_enter,
.finish = omap2_pm_finish,
.end = omap2_pm_end,
.valid = suspend_valid_only_mem,
};

66
arch/arm/mach-omap2/pm34xx.c
View File

@ -68,6 +68,9 @@ static inline bool is_suspending(void)
#define OMAP343X_TABLE_VALUE_OFFSET 0xc0
#define OMAP343X_CONTROL_REG_VALUE_OFFSET 0xc8
/* pm34xx errata defined in pm.h */
u16 pm34xx_errata;
struct power_state {
struct powerdomain *pwrdm;
u32 next_state;
@ -143,7 +146,7 @@ static void omap3_core_save_context(void)
/*
* Force write last pad into memory, as this can fail in some
* cases according to erratas 1.157, 1.185
* cases according to errata 1.157, 1.185
*/
omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
OMAP343X_CONTROL_MEM_WKUP + 0x2a0);
@ -430,7 +433,7 @@ void omap_sram_idle(void)
/*
* On EMU/HS devices ROM code restores a SRDC value
* from scratchpad which has automatic self refresh on timeout
* of AUTO_CNT = 1 enabled. This takes care of errata 1.142.
* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
* Hence store/restore the SDRC_POWER register here.
*/
if (omap_rev() >= OMAP3430_REV_ES3_0 &&
@ -529,12 +532,6 @@ out:
}
#ifdef CONFIG_SUSPEND
static int omap3_pm_prepare(void)
{
disable_hlt();
return 0;
}
static int omap3_pm_suspend(void)
{
struct power_state *pwrst;
@ -597,14 +594,10 @@ static int omap3_pm_enter(suspend_state_t unused)
return ret;
}
static void omap3_pm_finish(void)
{
enable_hlt();
}
/* Hooks to enable / disable UART interrupts during suspend */
static int omap3_pm_begin(suspend_state_t state)
{
disable_hlt();
suspend_state = state;
omap_uart_enable_irqs(0);
return 0;
@ -614,15 +607,14 @@ static void omap3_pm_end(void)
{
suspend_state = PM_SUSPEND_ON;
omap_uart_enable_irqs(1);
enable_hlt();
return;
}
static struct platform_suspend_ops omap_pm_ops = {
.begin = omap3_pm_begin,
.end = omap3_pm_end,
.prepare = omap3_pm_prepare,
.enter = omap3_pm_enter,
.finish = omap3_pm_finish,
.valid = suspend_valid_only_mem,
};
#endif /* CONFIG_SUSPEND */
@ -925,12 +917,29 @@ void omap3_pm_off_mode_enable(int enable)
state = PWRDM_POWER_RET;
#ifdef CONFIG_CPU_IDLE
omap3_cpuidle_update_states();
/*
* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
* enable OFF mode in a stable form for previous revisions, restrict
* instead to RET
*/
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
omap3_cpuidle_update_states(state, PWRDM_POWER_RET);
else
omap3_cpuidle_update_states(state, state);
#endif
list_for_each_entry(pwrst, &pwrst_list, node) {
pwrst->next_state = state;
omap_set_pwrdm_state(pwrst->pwrdm, state);
if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
pwrst->pwrdm == core_pwrdm &&
state == PWRDM_POWER_OFF) {
pwrst->next_state = PWRDM_POWER_RET;
WARN_ONCE(1,
"%s: Core OFF disabled due to errata i583\n",
__func__);
} else {
pwrst->next_state = state;
}
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
}
}
@ -1002,6 +1011,17 @@ void omap_push_sram_idle(void)
save_secure_ram_context_sz);
}
static void __init pm_errata_configure(void)
{
if (cpu_is_omap3630()) {
pm34xx_errata |= PM_RTA_ERRATUM_i608;
/* Enable the l2 cache toggling in sleep logic */
enable_omap3630_toggle_l2_on_restore();
if (omap_rev() < OMAP3630_REV_ES1_2)
pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
}
}
static int __init omap3_pm_init(void)
{
struct power_state *pwrst, *tmp;
@ -1011,6 +1031,8 @@ static int __init omap3_pm_init(void)
if (!cpu_is_omap34xx())
return -ENODEV;
pm_errata_configure();
printk(KERN_ERR "Power Management for TI OMAP3.\n");
/* XXX prcm_setup_regs needs to be before enabling hw
@ -1058,6 +1080,14 @@ static int __init omap3_pm_init(void)
pm_idle = omap3_pm_idle;
omap3_idle_init();
/*
* RTA is disabled during initialization as per erratum i608
* it is safer to disable RTA by the bootloader, but we would like
* to be doubly sure here and prevent any mishaps.
*/
if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
omap3630_ctrl_disable_rta();
clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
omap3_secure_ram_storage =

16
arch/arm/mach-omap2/pm44xx.c
View File

@ -31,12 +31,6 @@ struct power_state {
static LIST_HEAD(pwrst_list);
#ifdef CONFIG_SUSPEND
static int omap4_pm_prepare(void)
{
disable_hlt();
return 0;
}
static int omap4_pm_suspend(void)
{
do_wfi();
@ -59,28 +53,22 @@ static int omap4_pm_enter(suspend_state_t suspend_state)
return ret;
}
static void omap4_pm_finish(void)
{
enable_hlt();
return;
}
static int omap4_pm_begin(suspend_state_t state)
{
disable_hlt();
return 0;
}
static void omap4_pm_end(void)
{
enable_hlt();
return;
}
static struct platform_suspend_ops omap_pm_ops = {
.begin = omap4_pm_begin,
.end = omap4_pm_end,
.prepare = omap4_pm_prepare,
.enter = omap4_pm_enter,
.finish = omap4_pm_finish,
.valid = suspend_valid_only_mem,
};
#endif /* CONFIG_SUSPEND */

1
arch/arm/mach-omap2/sdrc.h
View File

@ -74,5 +74,4 @@ static inline u32 sms_read_reg(u16 reg)
*/
#define SDRC_MPURATE_LOOPS 96
#endif

1034
arch/arm/mach-omap2/sleep34xx.S
View File

File diff suppressed because it is too large Load Diff

7
arch/arm/mach-s3c2412/Kconfig
View File

@ -28,9 +28,16 @@ config S3C2412_DMA
config S3C2412_PM
bool
select S3C2412_PM_SLEEP
help
Internal config node to apply S3C2412 power management
config S3C2412_PM_SLEEP
bool
help
Internal config node to apply sleep for S3C2412 power management.
Can be selected by another SoCs with similar sleep procedure.
# Note, the S3C2412 IOtiming support is in plat-s3c24xx
config S3C2412_CPUFREQ

3
arch/arm/mach-s3c2412/Makefile
View File

@ -14,7 +14,8 @@ obj-$(CONFIG_CPU_S3C2412) += irq.o
obj-$(CONFIG_CPU_S3C2412) += clock.o
obj-$(CONFIG_CPU_S3C2412) += gpio.o
obj-$(CONFIG_S3C2412_DMA) += dma.o
obj-$(CONFIG_S3C2412_PM) += pm.o sleep.o
obj-$(CONFIG_S3C2412_PM) += pm.o
obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o
obj-$(CONFIG_S3C2412_CPUFREQ) += cpu-freq.o
# Machine support

1
arch/arm/mach-s3c2416/Kconfig
View File

@ -27,6 +27,7 @@ config S3C2416_DMA
config S3C2416_PM
bool
select S3C2412_PM_SLEEP
help
Internal config node to apply S3C2416 power management

6
arch/arm/mach-s5pv210/mach-aquila.c
View File

@ -378,6 +378,12 @@ static struct max8998_regulator_data aquila_regulators[] = {
static struct max8998_platform_data aquila_max8998_pdata = {
.num_regulators = ARRAY_SIZE(aquila_regulators),
.regulators = aquila_regulators,
.buck1_set1 = S5PV210_GPH0(3),
.buck1_set2 = S5PV210_GPH0(4),
.buck2_set3 = S5PV210_GPH0(5),
.buck1_max_voltage1 = 1200000,
.buck1_max_voltage2 = 1200000,
.buck2_max_voltage = 1200000,
};
#endif

6
arch/arm/mach-s5pv210/mach-goni.c
View File

@ -518,6 +518,12 @@ static struct max8998_regulator_data goni_regulators[] = {
static struct max8998_platform_data goni_max8998_pdata = {
.num_regulators = ARRAY_SIZE(goni_regulators),
.regulators = goni_regulators,
.buck1_set1 = S5PV210_GPH0(3),
.buck1_set2 = S5PV210_GPH0(4),
.buck2_set3 = S5PV210_GPH0(5),
.buck1_max_voltage1 = 1200000,
.buck1_max_voltage2 = 1200000,
.buck2_max_voltage = 1200000,
};
#endif

30
arch/arm/mach-shmobile/include/mach/entry-macro.S
View File

@ -1,4 +1,5 @@
/*
* Copyright (C) 2010 Magnus Damm
* Copyright (C) 2008 Renesas Solutions Corp.
*
* This program is free software; you can redistribute it and/or modify
@ -14,24 +15,45 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <mach/hardware.h>
#include <mach/irqs.h>
#define INTCA_BASE 0xe6980000
#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */
#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */
#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
#define INTLVLB_OFFS 0x00000034 /* previous priority level */
.macro disable_fiq
.endm
.macro get_irqnr_preamble, base, tmp
ldr \base, =INTFLGA
ldr \base, =INTCA_BASE
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqnr, [\base]
/* The single INTFLGA read access below results in the following:
*
* 1. INTLVLB is updated with old priority value from INTLVLA
* 2. Highest priority interrupt is accepted
* 3. INTLVLA is updated to contain priority of accepted interrupt
* 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
*/
ldr \irqnr, [\base, #INTFLGA_OFFS]
/* Restore INTLVLA with the value saved in INTLVLB.
* This is required to support interrupt priorities properly.
*/
ldrb \tmp, [\base, #INTLVLB_OFFS]
strb \tmp, [\base, #INTLVLA_OFFS]
/* Handle invalid vector number case */
cmp \irqnr, #0
beq 1000f
/* intevt to irq number */
/* Convert vector to irq number, same as the evt2irq() macro */
lsr \irqnr, \irqnr, #0x5
subs \irqnr, \irqnr, #16

2
arch/arm/mach-shmobile/include/mach/vmalloc.h
View File

@ -2,6 +2,6 @@
#define __ASM_MACH_VMALLOC_H
/* Vmalloc at ... - 0xe5ffffff */
#define VMALLOC_END 0xe6000000
#define VMALLOC_END 0xe6000000UL
#endif /* __ASM_MACH_VMALLOC_H */

699
arch/arm/plat-omap/dma.c
View File

File diff suppressed because it is too large Load Diff

232
arch/arm/plat-omap/include/plat/dma.h
View File

@ -21,142 +21,16 @@
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
#include <linux/platform_device.h>
/*
* TODO: These dma channel defines should go away once all
* the omap drivers hwmod adapted.
*/
/* Move omap4 specific defines to dma-44xx.h */
#include "dma-44xx.h"
/* Hardware registers for omap1 */
#define OMAP1_DMA_BASE (0xfffed800)
#define OMAP1_DMA_GCR 0x400
#define OMAP1_DMA_GSCR 0x404
#define OMAP1_DMA_GRST 0x408
#define OMAP1_DMA_HW_ID 0x442
#define OMAP1_DMA_PCH2_ID 0x444
#define OMAP1_DMA_PCH0_ID 0x446
#define OMAP1_DMA_PCH1_ID 0x448
#define OMAP1_DMA_PCHG_ID 0x44a
#define OMAP1_DMA_PCHD_ID 0x44c
#define OMAP1_DMA_CAPS_0_U 0x44e
#define OMAP1_DMA_CAPS_0_L 0x450
#define OMAP1_DMA_CAPS_1_U 0x452
#define OMAP1_DMA_CAPS_1_L 0x454
#define OMAP1_DMA_CAPS_2 0x456
#define OMAP1_DMA_CAPS_3 0x458
#define OMAP1_DMA_CAPS_4 0x45a
#define OMAP1_DMA_PCH2_SR 0x460
#define OMAP1_DMA_PCH0_SR 0x480
#define OMAP1_DMA_PCH1_SR 0x482
#define OMAP1_DMA_PCHD_SR 0x4c0
/* Hardware registers for omap2 and omap3 */
#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
#define OMAP44XX_DMA4_BASE (L4_44XX_BASE + 0x56000)
#define OMAP_DMA4_REVISION 0x00
#define OMAP_DMA4_GCR 0x78
#define OMAP_DMA4_IRQSTATUS_L0 0x08
#define OMAP_DMA4_IRQSTATUS_L1 0x0c
#define OMAP_DMA4_IRQSTATUS_L2 0x10
#define OMAP_DMA4_IRQSTATUS_L3 0x14
#define OMAP_DMA4_IRQENABLE_L0 0x18
#define OMAP_DMA4_IRQENABLE_L1 0x1c
#define OMAP_DMA4_IRQENABLE_L2 0x20
#define OMAP_DMA4_IRQENABLE_L3 0x24
#define OMAP_DMA4_SYSSTATUS 0x28
#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
#define OMAP_DMA4_CAPS_0 0x64
#define OMAP_DMA4_CAPS_2 0x6c
#define OMAP_DMA4_CAPS_3 0x70
#define OMAP_DMA4_CAPS_4 0x74
#define OMAP1_LOGICAL_DMA_CH_COUNT 17
#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
/* Common channel specific registers for omap1 */
#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
/* Common channel specific registers for omap2 */
#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
/* Channel specific registers only on omap1 */
#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
#define OMAP1_DMA_CCEN(n) 0
#define OMAP1_DMA_CCFN(n) 0
/* Channel specific registers only on omap2 */
#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
/* Additional registers available on OMAP4 */
#define OMAP_DMA4_CDP(n) (0x60 * (n) + 0xd0)
#define OMAP_DMA4_CNDP(n) (0x60 * (n) + 0xd4)
#define OMAP_DMA4_CCDN(n) (0x60 * (n) + 0xd8)
/* Dummy defines to keep multi-omap compiles happy */
#define OMAP1_DMA_REVISION 0
#define OMAP1_DMA_IRQSTATUS_L0 0
#define OMAP1_DMA_IRQENABLE_L0 0
#define OMAP1_DMA_OCP_SYSCONFIG 0
#define OMAP_DMA4_HW_ID 0
#define OMAP_DMA4_CAPS_0_L 0
#define OMAP_DMA4_CAPS_0_U 0
#define OMAP_DMA4_CAPS_1_L 0
#define OMAP_DMA4_CAPS_1_U 0
#define OMAP_DMA4_GSCR 0
#define OMAP_DMA4_CPC(n) 0
#define OMAP_DMA4_LCH_CTRL(n) 0
#define OMAP_DMA4_COLOR_L(n) 0
#define OMAP_DMA4_COLOR_U(n) 0
#define OMAP_DMA4_CCR2(n) 0
#define OMAP1_DMA_CSSA(n) 0
#define OMAP1_DMA_CDSA(n) 0
#define OMAP_DMA4_CSSA_L(n) 0
#define OMAP_DMA4_CSSA_U(n) 0
#define OMAP_DMA4_CDSA_L(n) 0
#define OMAP_DMA4_CDSA_U(n) 0
#define OMAP1_DMA_COLOR(n) 0
/*----------------------------------------------------------------------------*/
/* DMA channels for omap1 */
#define OMAP_DMA_NO_DEVICE 0
#define OMAP_DMA_MCSI1_TX 1
@ -405,6 +279,63 @@
#define DMA_CH_PRIO_HIGH 0x1
#define DMA_CH_PRIO_LOW 0x0 /* Def */
/* Errata handling */
#define IS_DMA_ERRATA(id) (errata & (id))
#define SET_DMA_ERRATA(id) (errata |= (id))
#define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
#define DMA_ERRATA_PARALLEL_CHANNELS BIT(0x1)
#define DMA_ERRATA_i378 BIT(0x2)
#define DMA_ERRATA_i541 BIT(0x3)
#define DMA_ERRATA_i88 BIT(0x4)
#define DMA_ERRATA_3_3 BIT(0x5)
#define DMA_ROMCODE_BUG BIT(0x6)
/* Attributes for OMAP DMA Contrller */
#define DMA_LINKED_LCH BIT(0x0)
#define GLOBAL_PRIORITY BIT(0x1)
#define RESERVE_CHANNEL BIT(0x2)
#define IS_CSSA_32 BIT(0x3)
#define IS_CDSA_32 BIT(0x4)
#define IS_RW_PRIORITY BIT(0x5)
#define ENABLE_1510_MODE BIT(0x6)
#define SRC_PORT BIT(0x7)
#define DST_PORT BIT(0x8)
#define SRC_INDEX BIT(0x9)
#define DST_INDEX BIT(0xA)
#define IS_BURST_ONLY4 BIT(0xB)
#define CLEAR_CSR_ON_READ BIT(0xC)
#define IS_WORD_16 BIT(0xD)
enum omap_reg_offsets {
GCR, GSCR, GRST1, HW_ID,
PCH2_ID, PCH0_ID, PCH1_ID, PCHG_ID,
PCHD_ID, CAPS_0, CAPS_1, CAPS_2,
CAPS_3, CAPS_4, PCH2_SR, PCH0_SR,
PCH1_SR, PCHD_SR, REVISION, IRQSTATUS_L0,
IRQSTATUS_L1, IRQSTATUS_L2, IRQSTATUS_L3, IRQENABLE_L0,
IRQENABLE_L1, IRQENABLE_L2, IRQENABLE_L3, SYSSTATUS,
OCP_SYSCONFIG,
/* omap1+ specific */
CPC, CCR2, LCH_CTRL,
/* Common registers for all omap's */
CSDP, CCR, CICR, CSR,
CEN, CFN, CSFI, CSEI,
CSAC, CDAC, CDEI,
CDFI, CLNK_CTRL,
/* Channel specific registers */
CSSA, CDSA, COLOR,
CCEN, CCFN,
/* omap3630 and omap4 specific */
CDP, CNDP, CCDN,
};
enum omap_dma_burst_mode {
OMAP_DMA_DATA_BURST_DIS = 0,
OMAP_DMA_DATA_BURST_4,
@ -470,6 +401,41 @@ struct omap_dma_channel_params {
#endif
};
struct omap_dma_lch {
int next_lch;
int dev_id;
u16 saved_csr;
u16 enabled_irqs;
const char *dev_name;
void (*callback)(int lch, u16 ch_status, void *data);
void *data;
long flags;
/* required for Dynamic chaining */
int prev_linked_ch;
int next_linked_ch;
int state;
int chain_id;
int status;
};
struct omap_dma_dev_attr {
u32 dev_caps;
u16 lch_count;
u16 chan_count;
struct omap_dma_lch *chan;
};
/* System DMA platform data structure */
struct omap_system_dma_plat_info {
struct omap_dma_dev_attr *dma_attr;
u32 errata;
void (*disable_irq_lch)(int lch);
void (*show_dma_caps)(void);
void (*clear_lch_regs)(int lch);
void (*clear_dma)(int lch);
void (*dma_write)(u32 val, int reg, int lch);
u32 (*dma_read)(int reg, int lch);
};
extern void omap_set_dma_priority(int lch, int dst_port, int priority);
extern int omap_request_dma(int dev_id, const char *dev_name,

35
arch/arm/plat-omap/include/plat/keypad.h
View File

@ -10,16 +10,18 @@
#ifndef ASMARM_ARCH_KEYPAD_H
#define ASMARM_ARCH_KEYPAD_H
#warning: Please update the board to use matrix_keypad.h instead
#ifndef CONFIG_ARCH_OMAP1
#warning Please update the board to use matrix-keypad driver
#endif
#include <linux/input/matrix_keypad.h>
struct omap_kp_platform_data {
int rows;
int cols;
int *keymap;
unsigned int keymapsize;
unsigned int rep:1;
const struct matrix_keymap_data *keymap_data;
bool rep;
unsigned long delay;
unsigned int dbounce:1;
bool dbounce;
/* specific to OMAP242x*/
unsigned int *row_gpios;
unsigned int *col_gpios;
@ -28,18 +30,21 @@ struct omap_kp_platform_data {
/* Group (0..3) -- when multiple keys are pressed, only the
* keys pressed in the same group are considered as pressed. This is
* in order to workaround certain crappy HW designs that produce ghost
* keypresses. */
#define GROUP_0 (0 << 16)
#define GROUP_1 (1 << 16)
#define GROUP_2 (2 << 16)
#define GROUP_3 (3 << 16)
* keypresses. Two free bits, not used by neither row/col nor keynum,
* must be available for use as group bits. The below GROUP_SHIFT
* macro definition is based on some prior knowledge of the
* matrix_keypad defined KEY() macro internals.
*/
#define GROUP_SHIFT 14
#define GROUP_0 (0 << GROUP_SHIFT)
#define GROUP_1 (1 << GROUP_SHIFT)
#define GROUP_2 (2 << GROUP_SHIFT)
#define GROUP_3 (3 << GROUP_SHIFT)
#define GROUP_MASK GROUP_3
#if KEY_MAX & GROUP_MASK
#error Group bits in conflict with keynum bits
#endif
#define KEY_PERSISTENT 0x00800000
#define KEYNUM_MASK 0x00EFFFFF
#define KEY(col, row, val) (((col) << 28) | ((row) << 24) | (val))
#define PERSISTENT_KEY(col, row) (((col) << 28) | ((row) << 24) | \
KEY_PERSISTENT)
#endif

31
arch/arm/plat-omap/include/plat/omap-pm.h
View File

@ -17,27 +17,10 @@
#include <linux/device.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <linux/opp.h>
#include "powerdomain.h"
/**
* struct omap_opp - clock frequency-to-OPP ID table for DSP, MPU
* @rate: target clock rate
* @opp_id: OPP ID
* @min_vdd: minimum VDD1 voltage (in millivolts) for this OPP
*
* Operating performance point data. Can vary by OMAP chip and board.
*/
struct omap_opp {
unsigned long rate;
u8 opp_id;
u16 min_vdd;
};
extern struct omap_opp *mpu_opps;
extern struct omap_opp *dsp_opps;
extern struct omap_opp *l3_opps;
/*
* agent_id values for use with omap_pm_set_min_bus_tput():
*
@ -59,9 +42,11 @@ extern struct omap_opp *l3_opps;
* framework starts. The "_if_" is to avoid name collisions with the
* PM idle-loop code.
*/
int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
struct omap_opp *dsp_opp_table,
struct omap_opp *l3_opp_table);
#ifdef CONFIG_OMAP_PM_NONE
#define omap_pm_if_early_init() 0
#else
int __init omap_pm_if_early_init(void);
#endif
/**
* omap_pm_if_init - OMAP PM init code called after clock fw init
@ -69,7 +54,11 @@ int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
* The main initialization code. OPP tables are passed in here. The
* "_if_" is to avoid name collisions with the PM idle-loop code.
*/
#ifdef CONFIG_OMAP_PM_NONE
#define omap_pm_if_init() 0
#else
int __init omap_pm_if_init(void);
#endif
/**
* omap_pm_if_exit - OMAP PM exit code

11
arch/arm/plat-omap/include/plat/sram.h
View File

@ -11,6 +11,7 @@
#ifndef __ARCH_ARM_OMAP_SRAM_H
#define __ARCH_ARM_OMAP_SRAM_H
#ifndef __ASSEMBLY__
extern void * omap_sram_push(void * start, unsigned long size);
extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
@ -74,4 +75,14 @@ extern void omap_push_sram_idle(void);
static inline void omap_push_sram_idle(void) {}
#endif /* CONFIG_PM */
#endif /* __ASSEMBLY__ */
/*
* OMAP2+: define the SRAM PA addresses.
* Used by the SRAM management code and the idle sleep code.
*/
#define OMAP2_SRAM_PA 0x40200000
#define OMAP3_SRAM_PA 0x40200000
#define OMAP4_SRAM_PA 0x40300000
#endif

1
arch/arm/plat-omap/include/plat/uncompress.h
View File

@ -146,6 +146,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
DEBUG_LL_OMAP3(3, cm_t35);
DEBUG_LL_OMAP3(3, cm_t3517);
DEBUG_LL_OMAP3(3, craneboard);
DEBUG_LL_OMAP3(3, devkit8000);
DEBUG_LL_OMAP3(3, igep0020);
DEBUG_LL_OMAP3(3, igep0030);
DEBUG_LL_OMAP3(3, nokia_rm680);

11
arch/arm/plat-omap/omap-pm-noop.c
View File

@ -26,10 +26,6 @@
#include <plat/powerdomain.h>
struct omap_opp *dsp_opps;
struct omap_opp *mpu_opps;
struct omap_opp *l3_opps;
/*
* Device-driver-originated constraints (via board-*.c files)
*/
@ -308,13 +304,8 @@ int omap_pm_get_dev_context_loss_count(struct device *dev)
/* Should be called before clk framework init */
int __init omap_pm_if_early_init(struct omap_opp *mpu_opp_table,
struct omap_opp *dsp_opp_table,
struct omap_opp *l3_opp_table)
int __init omap_pm_if_early_init(void)
{
mpu_opps = mpu_opp_table;
dsp_opps = dsp_opp_table;
l3_opps = l3_opp_table;
return 0;
}

7
arch/arm/plat-omap/sram.c
View File

@ -41,15 +41,12 @@
#define OMAP1_SRAM_PA 0x20000000
#define OMAP1_SRAM_VA VMALLOC_END
#define OMAP2_SRAM_PA 0x40200000
#define OMAP2_SRAM_PUB_PA 0x4020f800
#define OMAP2_SRAM_PUB_PA (OMAP2_SRAM_PA + 0xf800)
#define OMAP2_SRAM_VA 0xfe400000
#define OMAP2_SRAM_PUB_VA (OMAP2_SRAM_VA + 0x800)
#define OMAP3_SRAM_PA 0x40200000
#define OMAP3_SRAM_VA 0xfe400000
#define OMAP3_SRAM_PUB_PA 0x40208000
#define OMAP3_SRAM_PUB_PA (OMAP3_SRAM_PA + 0x8000)
#define OMAP3_SRAM_PUB_VA (OMAP3_SRAM_VA + 0x8000)
#define OMAP4_SRAM_PA 0x40300000
#define OMAP4_SRAM_VA 0xfe400000
#define OMAP4_SRAM_PUB_PA (OMAP4_SRAM_PA + 0x4000)
#define OMAP4_SRAM_PUB_VA (OMAP4_SRAM_VA + 0x4000)

2
arch/arm/plat-s3c24xx/Kconfig
View File

@ -8,7 +8,7 @@ config PLAT_S3C24XX
default y
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select S3C_DEVICE_NAND
select S3C_DEV_NAND
select S3C_GPIO_CFG_S3C24XX
help
Base platform code for any Samsung S3C24XX device

38
arch/mips/Kconfig
View File

@ -19,6 +19,8 @@ config MIPS
select GENERIC_ATOMIC64 if !64BIT
select HAVE_DMA_ATTRS
select HAVE_DMA_API_DEBUG
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_PROBE
menu "Machine selection"
@ -1664,6 +1666,28 @@ config PAGE_SIZE_64KB
endchoice
config FORCE_MAX_ZONEORDER
int "Maximum zone order"
range 13 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB
default "13" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_32KB
range 12 64 if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB
default "12" if SYS_SUPPORTS_HUGETLBFS && PAGE_SIZE_16KB
range 11 64
default "11"
help
The kernel memory allocator divides physically contiguous memory
blocks into "zones", where each zone is a power of two number of
pages. This option selects the largest power of two that the kernel
keeps in the memory allocator. If you need to allocate very large
blocks of physically contiguous memory, then you may need to
increase this value.
This config option is actually maximum order plus one. For example,
a value of 11 means that the largest free memory block is 2^10 pages.
The page size is not necessarily 4KB. Keep this in mind
when choosing a value for this option.
config BOARD_SCACHE
bool
@ -1921,20 +1945,6 @@ config CPU_R4000_WORKAROUNDS
config CPU_R4400_WORKAROUNDS
bool
#
# Use the generic interrupt handling code in kernel/irq/:
#
config GENERIC_HARDIRQS
bool
default y
config GENERIC_IRQ_PROBE
bool
default y
config IRQ_PER_CPU
bool
#
# - Highmem only makes sense for the 32-bit kernel.
# - The current highmem code will only work properly on physically indexed

2
arch/mips/alchemy/common/platform.c
View File

@ -27,6 +27,7 @@
static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
unsigned int old_state)
{
#ifdef CONFIG_SERIAL_8250
switch (state) {
case 0:
if ((__raw_readl(port->membase + UART_MOD_CNTRL) & 3) != 3) {
@ -49,6 +50,7 @@ static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
serial8250_do_pm(port, state, old_state);
break;
}
#endif
}
#define PORT(_base, _irq) \

5
arch/mips/alchemy/devboards/prom.c
View File

@ -54,10 +54,9 @@ void __init prom_init(void)
prom_init_cmdline();
memsize_str = prom_getenv("memsize");
if (!memsize_str)
if (!memsize_str || strict_strtoul(memsize_str, 0, &memsize))
memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;
else
strict_strtoul(memsize_str, 0, &memsize);
add_memory_region(0, memsize, BOOT_MEM_RAM);
}

9
arch/mips/ar7/clock.c
View File

@ -239,12 +239,12 @@ static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
calculate(base_clock, frequency, &prediv, &postdiv, &mul);
writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
msleep(1);
mdelay(1);
writel(4, &clock->pll);
while (readl(&clock->pll) & PLL_STATUS)
;
writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
msleep(75);
mdelay(75);
}
static void __init tnetd7300_init_clocks(void)
@ -456,7 +456,7 @@ void clk_put(struct clk *clk)
}
EXPORT_SYMBOL(clk_put);
int __init ar7_init_clocks(void)
void __init ar7_init_clocks(void)
{
switch (ar7_chip_id()) {
case AR7_CHIP_7100:
@ -472,7 +472,4 @@ int __init ar7_init_clocks(void)
}
/* adjust vbus clock rate */
vbus_clk.rate = bus_clk.rate / 2;
return 0;
}
arch_initcall(ar7_init_clocks);

3
arch/mips/ar7/time.c
View File

@ -30,6 +30,9 @@ void __init plat_time_init(void)
{
struct clk *cpu_clk;
/* Initialize ar7 clocks so the CPU clock frequency is correct */
ar7_init_clocks();
cpu_clk = clk_get(NULL, "cpu");
if (IS_ERR(cpu_clk)) {
printk(KERN_ERR "unable to get cpu clock\n");

151
arch/mips/bcm47xx/setup.c
View File

@ -32,7 +32,6 @@
#include <asm/reboot.h>
#include <asm/time.h>
#include <bcm47xx.h>
#include <asm/fw/cfe/cfe_api.h>
#include <asm/mach-bcm47xx/nvram.h>
struct ssb_bus ssb_bcm47xx;
@ -57,68 +56,112 @@ static void bcm47xx_machine_halt(void)
cpu_relax();
}
static void str2eaddr(char *str, char *dest)
#define READ_FROM_NVRAM(_outvar, name, buf) \
if (nvram_getenv(name, buf, sizeof(buf)) >= 0)\
sprom->_outvar = simple_strtoul(buf, NULL, 0);
static void bcm47xx_fill_sprom(struct ssb_sprom *sprom)
{
int i = 0;
char buf[100];
u32 boardflags;
if (str == NULL) {
memset(dest, 0, 6);
return;
memset(sprom, 0, sizeof(struct ssb_sprom));
sprom->revision = 1; /* Fallback: Old hardware does not define this. */
READ_FROM_NVRAM(revision, "sromrev", buf);
if (nvram_getenv("il0macaddr", buf, sizeof(buf)) >= 0)
nvram_parse_macaddr(buf, sprom->il0mac);
if (nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
nvram_parse_macaddr(buf, sprom->et0mac);
if (nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
nvram_parse_macaddr(buf, sprom->et1mac);
READ_FROM_NVRAM(et0phyaddr, "et0phyaddr", buf);
READ_FROM_NVRAM(et1phyaddr, "et1phyaddr", buf);
READ_FROM_NVRAM(et0mdcport, "et0mdcport", buf);
READ_FROM_NVRAM(et1mdcport, "et1mdcport", buf);
READ_FROM_NVRAM(board_rev, "boardrev", buf);
READ_FROM_NVRAM(country_code, "ccode", buf);
READ_FROM_NVRAM(ant_available_a, "aa5g", buf);
READ_FROM_NVRAM(ant_available_bg, "aa2g", buf);
READ_FROM_NVRAM(pa0b0, "pa0b0", buf);
READ_FROM_NVRAM(pa0b1, "pa0b1", buf);
READ_FROM_NVRAM(pa0b2, "pa0b2", buf);
READ_FROM_NVRAM(pa1b0, "pa1b0", buf);
READ_FROM_NVRAM(pa1b1, "pa1b1", buf);
READ_FROM_NVRAM(pa1b2, "pa1b2", buf);
READ_FROM_NVRAM(pa1lob0, "pa1lob0", buf);
READ_FROM_NVRAM(pa1lob2, "pa1lob1", buf);
READ_FROM_NVRAM(pa1lob1, "pa1lob2", buf);
READ_FROM_NVRAM(pa1hib0, "pa1hib0", buf);
READ_FROM_NVRAM(pa1hib2, "pa1hib1", buf);
READ_FROM_NVRAM(pa1hib1, "pa1hib2", buf);
READ_FROM_NVRAM(gpio0, "wl0gpio0", buf);
READ_FROM_NVRAM(gpio1, "wl0gpio1", buf);
READ_FROM_NVRAM(gpio2, "wl0gpio2", buf);
READ_FROM_NVRAM(gpio3, "wl0gpio3", buf);
READ_FROM_NVRAM(maxpwr_bg, "pa0maxpwr", buf);
READ_FROM_NVRAM(maxpwr_al, "pa1lomaxpwr", buf);
READ_FROM_NVRAM(maxpwr_a, "pa1maxpwr", buf);
READ_FROM_NVRAM(maxpwr_ah, "pa1himaxpwr", buf);
READ_FROM_NVRAM(itssi_a, "pa1itssit", buf);
READ_FROM_NVRAM(itssi_bg, "pa0itssit", buf);
READ_FROM_NVRAM(tri2g, "tri2g", buf);
READ_FROM_NVRAM(tri5gl, "tri5gl", buf);
READ_FROM_NVRAM(tri5g, "tri5g", buf);
READ_FROM_NVRAM(tri5gh, "tri5gh", buf);
READ_FROM_NVRAM(rxpo2g, "rxpo2g", buf);
READ_FROM_NVRAM(rxpo5g, "rxpo5g", buf);
READ_FROM_NVRAM(rssisav2g, "rssisav2g", buf);
READ_FROM_NVRAM(rssismc2g, "rssismc2g", buf);
READ_FROM_NVRAM(rssismf2g, "rssismf2g", buf);
READ_FROM_NVRAM(bxa2g, "bxa2g", buf);
READ_FROM_NVRAM(rssisav5g, "rssisav5g", buf);
READ_FROM_NVRAM(rssismc5g, "rssismc5g", buf);
READ_FROM_NVRAM(rssismf5g, "rssismf5g", buf);
READ_FROM_NVRAM(bxa5g, "bxa5g", buf);
READ_FROM_NVRAM(cck2gpo, "cck2gpo", buf);
READ_FROM_NVRAM(ofdm2gpo, "ofdm2gpo", buf);
READ_FROM_NVRAM(ofdm5glpo, "ofdm5glpo", buf);
READ_FROM_NVRAM(ofdm5gpo, "ofdm5gpo", buf);
READ_FROM_NVRAM(ofdm5ghpo, "ofdm5ghpo", buf);
if (nvram_getenv("boardflags", buf, sizeof(buf)) >= 0) {
boardflags = simple_strtoul(buf, NULL, 0);
if (boardflags) {
sprom->boardflags_lo = (boardflags & 0x0000FFFFU);
sprom->boardflags_hi = (boardflags & 0xFFFF0000U) >> 16;
}
}
for (;;) {
dest[i++] = (char) simple_strtoul(str, NULL, 16);
str += 2;
if (!*str++ || i == 6)
break;
if (nvram_getenv("boardflags2", buf, sizeof(buf)) >= 0) {
boardflags = simple_strtoul(buf, NULL, 0);
if (boardflags) {
sprom->boardflags2_lo = (boardflags & 0x0000FFFFU);
sprom->boardflags2_hi = (boardflags & 0xFFFF0000U) >> 16;
}
}
}
static int bcm47xx_get_invariants(struct ssb_bus *bus,
struct ssb_init_invariants *iv)
{
char buf[100];
char buf[20];
/* Fill boardinfo structure */
memset(&(iv->boardinfo), 0 , sizeof(struct ssb_boardinfo));
if (cfe_getenv("boardvendor", buf, sizeof(buf)) >= 0 ||
nvram_getenv("boardvendor", buf, sizeof(buf)) >= 0)
if (nvram_getenv("boardvendor", buf, sizeof(buf)) >= 0)
iv->boardinfo.vendor = (u16)simple_strtoul(buf, NULL, 0);
else
iv->boardinfo.vendor = SSB_BOARDVENDOR_BCM;
if (nvram_getenv("boardtype", buf, sizeof(buf)) >= 0)
iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
if (cfe_getenv("boardtype", buf, sizeof(buf)) >= 0 ||
nvram_getenv("boardtype", buf, sizeof(buf)) >= 0)
iv->boardinfo.type = (u16)simple_strtoul(buf, NULL, 0);
if (cfe_getenv("boardrev", buf, sizeof(buf)) >= 0 ||
nvram_getenv("boardrev", buf, sizeof(buf)) >= 0)
if (nvram_getenv("boardrev", buf, sizeof(buf)) >= 0)
iv->boardinfo.rev = (u16)simple_strtoul(buf, NULL, 0);
/* Fill sprom structure */
memset(&(iv->sprom), 0, sizeof(struct ssb_sprom));
iv->sprom.revision = 3;
bcm47xx_fill_sprom(&iv->sprom);
if (cfe_getenv("et0macaddr", buf, sizeof(buf)) >= 0 ||
nvram_getenv("et0macaddr", buf, sizeof(buf)) >= 0)
str2eaddr(buf, iv->sprom.et0mac);
if (cfe_getenv("et1macaddr", buf, sizeof(buf)) >= 0 ||
nvram_getenv("et1macaddr", buf, sizeof(buf)) >= 0)
str2eaddr(buf, iv->sprom.et1mac);
if (cfe_getenv("et0phyaddr", buf, sizeof(buf)) >= 0 ||
nvram_getenv("et0phyaddr", buf, sizeof(buf)) >= 0)
iv->sprom.et0phyaddr = simple_strtoul(buf, NULL, 0);
if (cfe_getenv("et1phyaddr", buf, sizeof(buf)) >= 0 ||
nvram_getenv("et1phyaddr", buf, sizeof(buf)) >= 0)
iv->sprom.et1phyaddr = simple_strtoul(buf, NULL, 0);
if (cfe_getenv("et0mdcport", buf, sizeof(buf)) >= 0 ||
nvram_getenv("et0mdcport", buf, sizeof(buf)) >= 0)
iv->sprom.et0mdcport = simple_strtoul(buf, NULL, 10);
if (cfe_getenv("et1mdcport", buf, sizeof(buf)) >= 0 ||
nvram_getenv("et1mdcport", buf, sizeof(buf)) >= 0)
iv->sprom.et1mdcport = simple_strtoul(buf, NULL, 10);
if (nvram_getenv("cardbus", buf, sizeof(buf)) >= 0)
iv->has_cardbus_slot = !!simple_strtoul(buf, NULL, 10);
return 0;
}
@ -126,12 +169,28 @@ static int bcm47xx_get_invariants(struct ssb_bus *bus,
void __init plat_mem_setup(void)
{
int err;
char buf[100];
struct ssb_mipscore *mcore;
err = ssb_bus_ssbbus_register(&ssb_bcm47xx, SSB_ENUM_BASE,
bcm47xx_get_invariants);
if (err)
panic("Failed to initialize SSB bus (err %d)\n", err);
mcore = &ssb_bcm47xx.mipscore;
if (nvram_getenv("kernel_args", buf, sizeof(buf)) >= 0) {
if (strstr(buf, "console=ttyS1")) {
struct ssb_serial_port port;
printk(KERN_DEBUG "Swapping serial ports!\n");
/* swap serial ports */
memcpy(&port, &mcore->serial_ports[0], sizeof(port));
memcpy(&mcore->serial_ports[0], &mcore->serial_ports[1],
sizeof(port));
memcpy(&mcore->serial_ports[1], &port, sizeof(port));
}
}
_machine_restart = bcm47xx_machine_restart;
_machine_halt = bcm47xx_machine_halt;
pm_power_off = bcm47xx_machine_halt;

4
arch/mips/include/asm/cpu.h
View File

@ -111,8 +111,8 @@
* These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
*/
#define PRID_IMP_BMIPS4KC 0x4000
#define PRID_IMP_BMIPS32 0x8000
#define PRID_IMP_BMIPS32_REV4 0x4000
#define PRID_IMP_BMIPS32_REV8 0x8000
#define PRID_IMP_BMIPS3300 0x9000
#define PRID_IMP_BMIPS3300_ALT 0x9100
#define PRID_IMP_BMIPS3300_BUG 0x0000

8
arch/mips/include/asm/elf.h
View File

@ -249,7 +249,8 @@ extern struct mips_abi mips_abi_n32;
#define SET_PERSONALITY(ex) \
do { \
set_personality(PER_LINUX); \
if (personality(current->personality) != PER_LINUX) \
set_personality(PER_LINUX); \
\
current->thread.abi = &mips_abi; \
} while (0)
@ -296,6 +297,8 @@ do { \
#define SET_PERSONALITY(ex) \
do { \
unsigned int p; \
\
clear_thread_flag(TIF_32BIT_REGS); \
clear_thread_flag(TIF_32BIT_ADDR); \
\
@ -304,7 +307,8 @@ do { \
else \
current->thread.abi = &mips_abi; \
\
if (current->personality != PER_LINUX32) \
p = personality(current->personality); \
if (p != PER_LINUX32 && p != PER_LINUX) \
set_personality(PER_LINUX); \
} while (0)

12
arch/mips/include/asm/io.h
View File

@ -329,10 +329,14 @@ static inline void pfx##write##bwlq(type val, \
"dsrl32 %L0, %L0, 0" "\n\t" \
"dsll32 %M0, %M0, 0" "\n\t" \
"or %L0, %L0, %M0" "\n\t" \
".set push" "\n\t" \
".set noreorder" "\n\t" \
".set nomacro" "\n\t" \
"sd %L0, %2" "\n\t" \
".set pop" "\n\t" \
".set mips0" "\n" \
: "=r" (__tmp) \
: "0" (__val), "m" (*__mem)); \
: "0" (__val), "R" (*__mem)); \
if (irq) \
local_irq_restore(__flags); \
} else \
@ -355,12 +359,16 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \
local_irq_save(__flags); \
__asm__ __volatile__( \
".set mips3" "\t\t# __readq" "\n\t" \
".set push" "\n\t" \
".set noreorder" "\n\t" \
".set nomacro" "\n\t" \
"ld %L0, %1" "\n\t" \
".set pop" "\n\t" \
"dsra32 %M0, %L0, 0" "\n\t" \
"sll %L0, %L0, 0" "\n\t" \
".set mips0" "\n" \
: "=r" (__val) \
: "m" (*__mem)); \
: "R" (*__mem)); \
if (irq) \
local_irq_restore(__flags); \
} else { \

3
arch/mips/include/asm/mach-ar7/ar7.h
View File

@ -201,7 +201,6 @@ static inline void ar7_device_off(u32 bit)
}
int __init ar7_gpio_init(void);
int __init ar7_gpio_init(void);
void __init ar7_init_clocks(void);
#endif /* __AR7_H__ */

7
arch/mips/include/asm/mach-bcm47xx/nvram.h
View File

@ -12,6 +12,7 @@
#define __NVRAM_H
#include <linux/types.h>
#include <linux/kernel.h>
struct nvram_header {
u32 magic;
@ -36,4 +37,10 @@ struct nvram_header {
extern int nvram_getenv(char *name, char *val, size_t val_len);
static inline void nvram_parse_macaddr(char *buf, u8 *macaddr)
{
sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0], &macaddr[1],
&macaddr[2], &macaddr[3], &macaddr[4], &macaddr[5]);
}
#endif

4
arch/mips/jz4740/board-qi_lb60.c
View File

@ -5,7 +5,7 @@
*
* Copyright (c) 2009 Qi Hardware inc.,
* Author: Xiangfu Liu <xiangfu@qi-hardware.com>
* Copyright 2010, Lars-Petrer Clausen <lars@metafoo.de>
* Copyright 2010, Lars-Peter Clausen <lars@metafoo.de>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 or later
@ -235,7 +235,7 @@ static const unsigned int qi_lb60_keypad_rows[] = {
QI_LB60_GPIO_KEYIN(3),
QI_LB60_GPIO_KEYIN(4),
QI_LB60_GPIO_KEYIN(5),
QI_LB60_GPIO_KEYIN(7),
QI_LB60_GPIO_KEYIN(6),
QI_LB60_GPIO_KEYIN8,
};

2
arch/mips/jz4740/platform.c
View File

@ -208,7 +208,7 @@ struct platform_device jz4740_i2s_device = {
/* PCM */
struct platform_device jz4740_pcm_device = {
.name = "jz4740-pcm",
.name = "jz4740-pcm-audio",
.id = -1,
};

2
arch/mips/jz4740/prom.c
View File

@ -23,7 +23,7 @@
#include <asm/bootinfo.h>
#include <asm/mach-jz4740/base.h>
void jz4740_init_cmdline(int argc, char *argv[])
static __init void jz4740_init_cmdline(int argc, char *argv[])
{
unsigned int count = COMMAND_LINE_SIZE - 1;
int i;

2
arch/mips/kernel/cevt-r4k.c
View File

@ -32,7 +32,7 @@ static int mips_next_event(unsigned long delta,
cnt = read_c0_count();
cnt += delta;
write_c0_compare(cnt);
res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
return res;
}

7
arch/mips/kernel/cpu-probe.c
View File

@ -905,7 +905,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
{
decode_configs(c);
switch (c->processor_id & 0xff00) {
case PRID_IMP_BMIPS32:
case PRID_IMP_BMIPS32_REV4:
case PRID_IMP_BMIPS32_REV8:
c->cputype = CPU_BMIPS32;
__cpu_name[cpu] = "Broadcom BMIPS32";
break;
@ -933,10 +934,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "Broadcom BMIPS5000";
c->options |= MIPS_CPU_ULRI;
break;
case PRID_IMP_BMIPS4KC:
c->cputype = CPU_4KC;
__cpu_name[cpu] = "MIPS 4Kc";
break;
}
}

13
arch/mips/kernel/linux32.c
View File

@ -251,14 +251,15 @@ SYSCALL_DEFINE5(n32_msgrcv, int, msqid, u32, msgp, size_t, msgsz,
SYSCALL_DEFINE1(32_personality, unsigned long, personality)
{
unsigned int p = personality & 0xffffffff;
int ret;
personality &= 0xffffffff;
if (personality(current->personality) == PER_LINUX32 &&
personality == PER_LINUX)
personality = PER_LINUX32;
ret = sys_personality(personality);
if (ret == PER_LINUX32)
ret = PER_LINUX;
personality(p) == PER_LINUX)
p = (p & ~PER_MASK) | PER_LINUX32;
ret = sys_personality(p);
if (ret != -1 && personality(ret) == PER_LINUX32)
ret = (ret & ~PER_MASK) | PER_LINUX;
return ret;
}

1
arch/mips/kernel/process.c
View File

@ -142,7 +142,6 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
childregs->regs[7] = 0; /* Clear error flag */
childregs->regs[2] = 0; /* Child gets zero as return value */
regs->regs[2] = p->pid;
if (childregs->cp0_status & ST0_CU0) {
childregs->regs[28] = (unsigned long) ti;

2
arch/mips/kernel/prom.c
View File

@ -100,7 +100,7 @@ void __init device_tree_init(void)
return;
base = virt_to_phys((void *)initial_boot_params);
size = initial_boot_params->totalsize;
size = be32_to_cpu(initial_boot_params->totalsize);
/* Before we do anything, lets reserve the dt blob */
reserve_mem_mach(base, size);

2
arch/mips/kernel/smp-mt.c
View File

@ -153,7 +153,7 @@ static void __cpuinit vsmp_init_secondary(void)
{
extern int gic_present;
/* This is Malta specific: IPI,performance and timer inetrrupts */
/* This is Malta specific: IPI,performance and timer interrupts */
if (gic_present)
change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
STATUSF_IP6 | STATUSF_IP7);

44
arch/mips/kernel/traps.c
View File

@ -83,7 +83,8 @@ extern asmlinkage void handle_mcheck(void);
extern asmlinkage void handle_reserved(void);
extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
struct mips_fpu_struct *ctx, int has_fpu);
struct mips_fpu_struct *ctx, int has_fpu,
void *__user *fault_addr);
void (*board_be_init)(void);
int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
@ -661,12 +662,36 @@ asmlinkage void do_ov(struct pt_regs *regs)
force_sig_info(SIGFPE, &info, current);
}
static int process_fpemu_return(int sig, void __user *fault_addr)
{
if (sig == SIGSEGV || sig == SIGBUS) {
struct siginfo si = {0};
si.si_addr = fault_addr;
si.si_signo = sig;
if (sig == SIGSEGV) {
if (find_vma(current->mm, (unsigned long)fault_addr))
si.si_code = SEGV_ACCERR;
else
si.si_code = SEGV_MAPERR;
} else {
si.si_code = BUS_ADRERR;
}
force_sig_info(sig, &si, current);
return 1;
} else if (sig) {
force_sig(sig, current);
return 1;
} else {
return 0;
}
}
/*
* XXX Delayed fp exceptions when doing a lazy ctx switch XXX
*/
asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
{
siginfo_t info;
siginfo_t info = {0};
if (notify_die(DIE_FP, "FP exception", regs, 0, regs_to_trapnr(regs), SIGFPE)
== NOTIFY_STOP)
@ -675,6 +700,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
if (fcr31 & FPU_CSR_UNI_X) {
int sig;
void __user *fault_addr = NULL;
/*
* Unimplemented operation exception. If we've got the full
@ -690,7 +716,8 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
lose_fpu(1);
/* Run the emulator */
sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1);
sig = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
&fault_addr);
/*
* We can't allow the emulated instruction to leave any of
@ -702,8 +729,7 @@ asmlinkage void do_fpe(struct pt_regs *regs, unsigned long fcr31)
own_fpu(1); /* Using the FPU again. */
/* If something went wrong, signal */
if (sig)
force_sig(sig, current);
process_fpemu_return(sig, fault_addr);
return;
} else if (fcr31 & FPU_CSR_INV_X)
@ -996,11 +1022,11 @@ asmlinkage void do_cpu(struct pt_regs *regs)
if (!raw_cpu_has_fpu) {
int sig;
void __user *fault_addr = NULL;
sig = fpu_emulator_cop1Handler(regs,
&current->thread.fpu, 0);
if (sig)
force_sig(sig, current);
else
&current->thread.fpu,
0, &fault_addr);
if (!process_fpemu_return(sig, fault_addr))
mt_ase_fp_affinity();
}

14
arch/mips/kernel/vpe.c
View File

@ -1092,6 +1092,10 @@ static int vpe_open(struct inode *inode, struct file *filp)
/* this of-course trashes what was there before... */
v->pbuffer = vmalloc(P_SIZE);
if (!v->pbuffer) {
pr_warning("VPE loader: unable to allocate memory\n");
return -ENOMEM;
}
v->plen = P_SIZE;
v->load_addr = NULL;
v->len = 0;
@ -1149,10 +1153,9 @@ static int vpe_release(struct inode *inode, struct file *filp)
if (ret < 0)
v->shared_ptr = NULL;
// cleanup any temp buffers
if (v->pbuffer)
vfree(v->pbuffer);
vfree(v->pbuffer);
v->plen = 0;
return ret;
}
@ -1169,11 +1172,6 @@ static ssize_t vpe_write(struct file *file, const char __user * buffer,
if (v == NULL)
return -ENODEV;
if (v->pbuffer == NULL) {
printk(KERN_ERR "VPE loader: no buffer for program\n");
return -ENOMEM;
}
if ((count + v->len) > v->plen) {
printk(KERN_WARNING
"VPE loader: elf size too big. Perhaps strip uneeded symbols\n");

4
arch/mips/lib/memset.S
View File

@ -161,16 +161,16 @@ FEXPORT(__bzero)
.Lfwd_fixup:
PTR_L t0, TI_TASK($28)
LONG_L t0, THREAD_BUADDR(t0)
andi a2, 0x3f
LONG_L t0, THREAD_BUADDR(t0)
LONG_ADDU a2, t1
jr ra
LONG_SUBU a2, t0
.Lpartial_fixup:
PTR_L t0, TI_TASK($28)
LONG_L t0, THREAD_BUADDR(t0)
andi a2, LONGMASK
LONG_L t0, THREAD_BUADDR(t0)
LONG_ADDU a2, t1
jr ra
LONG_SUBU a2, t0

4
arch/mips/loongson/common/env.c
View File

@ -29,9 +29,9 @@ unsigned long memsize, highmemsize;
#define parse_even_earlier(res, option, p) \
do { \
int ret; \
if (strncmp(option, (char *)p, strlen(option)) == 0) \
strict_strtol((char *)p + strlen(option"="), \
10, &res); \
ret = strict_strtol((char *)p + strlen(option"="), 10, &res); \
} while (0)
void __init prom_init_env(void)

116
arch/mips/math-emu/cp1emu.c
View File

@ -64,7 +64,7 @@ static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
#if __mips >= 4 && __mips != 32
static int fpux_emu(struct pt_regs *,
struct mips_fpu_struct *, mips_instruction);
struct mips_fpu_struct *, mips_instruction, void *__user *);
#endif
/* Further private data for which no space exists in mips_fpu_struct */
@ -208,16 +208,23 @@ static inline int cop1_64bit(struct pt_regs *xcp)
* Two instructions if the instruction is in a branch delay slot.
*/
static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
void *__user *fault_addr)
{
mips_instruction ir;
unsigned long emulpc, contpc;
unsigned int cond;
if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = (mips_instruction __user *)xcp->cp0_epc;
return SIGBUS;
}
if (__get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = (mips_instruction __user *)xcp->cp0_epc;
return SIGSEGV;
}
/* XXX NEC Vr54xx bug workaround */
if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir))
@ -245,10 +252,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
#endif
return SIGILL;
}
if (get_user(ir, (mips_instruction __user *) emulpc)) {
if (!access_ok(VERIFY_READ, emulpc, sizeof(mips_instruction))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = (mips_instruction __user *)emulpc;
return SIGBUS;
}
if (__get_user(ir, (mips_instruction __user *) emulpc)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = (mips_instruction __user *)emulpc;
return SIGSEGV;
}
/* __compute_return_epc() will have updated cp0_epc */
contpc = xcp->cp0_epc;
/* In order not to confuse ptrace() et al, tweak context */
@ -269,10 +282,17 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
u64 val;
MIPS_FPU_EMU_INC_STATS(loads);
if (get_user(val, va)) {
if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGBUS;
}
if (__get_user(val, va)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGSEGV;
}
DITOREG(val, MIPSInst_RT(ir));
break;
}
@ -284,10 +304,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
MIPS_FPU_EMU_INC_STATS(stores);
DIFROMREG(val, MIPSInst_RT(ir));
if (put_user(val, va)) {
if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGBUS;
}
if (__put_user(val, va)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGSEGV;
}
break;
}
@ -297,10 +323,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
u32 val;
MIPS_FPU_EMU_INC_STATS(loads);
if (get_user(val, va)) {
if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGBUS;
}
if (__get_user(val, va)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGSEGV;
}
SITOREG(val, MIPSInst_RT(ir));
break;
}
@ -312,10 +344,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
MIPS_FPU_EMU_INC_STATS(stores);
SIFROMREG(val, MIPSInst_RT(ir));
if (put_user(val, va)) {
if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGBUS;
}
if (__put_user(val, va)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGSEGV;
}
break;
}
@ -440,10 +478,17 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
contpc = (xcp->cp0_epc +
(MIPSInst_SIMM(ir) << 2));
if (get_user(ir,
if (!access_ok(VERIFY_READ, xcp->cp0_epc,
sizeof(mips_instruction))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = (mips_instruction __user *)xcp->cp0_epc;
return SIGBUS;
}
if (__get_user(ir,
(mips_instruction __user *) xcp->cp0_epc)) {
MIPS_FPU_EMU_INC_STATS(errors);
return SIGBUS;
*fault_addr = (mips_instruction __user *)xcp->cp0_epc;
return SIGSEGV;
}
switch (MIPSInst_OPCODE(ir)) {
@ -506,9 +551,8 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx)
#if __mips >= 4 && __mips != 32
case cop1x_op:{
int sig;
if ((sig = fpux_emu(xcp, ctx, ir)))
int sig = fpux_emu(xcp, ctx, ir, fault_addr);
if (sig)
return sig;
break;
}
@ -604,7 +648,7 @@ DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
mips_instruction ir)
mips_instruction ir, void *__user *fault_addr)
{
unsigned rcsr = 0; /* resulting csr */
@ -624,10 +668,16 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
xcp->regs[MIPSInst_FT(ir)]);
MIPS_FPU_EMU_INC_STATS(loads);
if (get_user(val, va)) {
if (!access_ok(VERIFY_READ, va, sizeof(u32))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGBUS;
}
if (__get_user(val, va)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGSEGV;
}
SITOREG(val, MIPSInst_FD(ir));
break;
@ -638,9 +688,15 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
MIPS_FPU_EMU_INC_STATS(stores);
SIFROMREG(val, MIPSInst_FS(ir));
if (!access_ok(VERIFY_WRITE, va, sizeof(u32))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGBUS;
}
if (put_user(val, va)) {
MIPS_FPU_EMU_INC_STATS(errors);
return SIGBUS;
*fault_addr = va;
return SIGSEGV;
}
break;
@ -701,10 +757,16 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
xcp->regs[MIPSInst_FT(ir)]);
MIPS_FPU_EMU_INC_STATS(loads);
if (get_user(val, va)) {
if (!access_ok(VERIFY_READ, va, sizeof(u64))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGBUS;
}
if (__get_user(val, va)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGSEGV;
}
DITOREG(val, MIPSInst_FD(ir));
break;
@ -714,10 +776,16 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
MIPS_FPU_EMU_INC_STATS(stores);
DIFROMREG(val, MIPSInst_FS(ir));
if (put_user(val, va)) {
if (!access_ok(VERIFY_WRITE, va, sizeof(u64))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGBUS;
}
if (__put_user(val, va)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = va;
return SIGSEGV;
}
break;
case madd_d_op:
@ -1242,7 +1310,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
}
int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
int has_fpu)
int has_fpu, void *__user *fault_addr)
{
unsigned long oldepc, prevepc;
mips_instruction insn;
@ -1252,10 +1320,16 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
do {
prevepc = xcp->cp0_epc;
if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
if (!access_ok(VERIFY_READ, xcp->cp0_epc, sizeof(mips_instruction))) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = (mips_instruction __user *)xcp->cp0_epc;
return SIGBUS;
}
if (__get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) {
MIPS_FPU_EMU_INC_STATS(errors);
*fault_addr = (mips_instruction __user *)xcp->cp0_epc;
return SIGSEGV;
}
if (insn == 0)
xcp->cp0_epc += 4; /* skip nops */
else {
@ -1267,7 +1341,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
*/
/* convert to ieee library modes */
ieee754_csr.rm = ieee_rm[ieee754_csr.rm];
sig = cop1Emulate(xcp, ctx);
sig = cop1Emulate(xcp, ctx, fault_addr);
/* revert to mips rounding mode */
ieee754_csr.rm = mips_rm[ieee754_csr.rm];
}

4
arch/mips/mm/dma-default.c
View File

@ -288,7 +288,7 @@ int mips_dma_supported(struct device *dev, u64 mask)
return plat_dma_supported(dev, mask);
}
void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
@ -298,6 +298,8 @@ void mips_dma_cache_sync(struct device *dev, void *vaddr, size_t size,
__dma_sync((unsigned long)vaddr, size, direction);
}
EXPORT_SYMBOL(dma_cache_sync);
static struct dma_map_ops mips_default_dma_map_ops = {
.alloc_coherent = mips_dma_alloc_coherent,
.free_coherent = mips_dma_free_coherent,

4
arch/mips/mm/sc-mips.c
View File

@ -68,6 +68,9 @@ static struct bcache_ops mips_sc_ops = {
*/
static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
{
unsigned int config2 = read_c0_config2();
unsigned int tmp;
/* Check the bypass bit (L2B) */
switch (c->cputype) {
case CPU_34K:
@ -83,6 +86,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
c->scache.linesz = 2 << tmp;
else
return 0;
return 1;
}
static inline int __init mips_sc_probe(void)

12
arch/mips/pmc-sierra/yosemite/py-console.c
View File

@ -65,11 +65,15 @@ static unsigned char readb_outer_space(unsigned long long phys)
__asm__ __volatile__ (
" .set mips3 \n"
" .set push \n"
" .set noreorder \n"
" .set nomacro \n"
" ld %0, %1 \n"
" .set pop \n"
" lbu %0, (%0) \n"
" .set mips0 \n"
: "=r" (res)
: "m" (vaddr));
: "R" (vaddr));
write_c0_status(sr);
ssnop_4();
@ -89,11 +93,15 @@ static void writeb_outer_space(unsigned long long phys, unsigned char c)
__asm__ __volatile__ (
" .set mips3 \n"
" .set push \n"
" .set noreorder \n"
" .set nomacro \n"
" ld %0, %1 \n"
" .set pop \n"
" sb %2, (%0) \n"
" .set mips0 \n"
: "=&r" (tmp)
: "m" (vaddr), "r" (c));
: "R" (vaddr), "r" (c));
write_c0_status(sr);
ssnop_4();

8
arch/mips/sibyte/swarm/setup.c
View File

@ -82,7 +82,7 @@ int swarm_be_handler(struct pt_regs *regs, int is_fixup)
enum swarm_rtc_type {
RTC_NONE,
RTC_XICOR,
RTC_M4LT81
RTC_M41T81,
};
enum swarm_rtc_type swarm_rtc_type;
@ -96,7 +96,7 @@ void read_persistent_clock(struct timespec *ts)
sec = xicor_get_time();
break;
case RTC_M4LT81:
case RTC_M41T81:
sec = m41t81_get_time();
break;
@ -115,7 +115,7 @@ int rtc_mips_set_time(unsigned long sec)
case RTC_XICOR:
return xicor_set_time(sec);
case RTC_M4LT81:
case RTC_M41T81:
return m41t81_set_time(sec);
case RTC_NONE:
@ -141,7 +141,7 @@ void __init plat_mem_setup(void)
if (xicor_probe())
swarm_rtc_type = RTC_XICOR;
if (m41t81_probe())
swarm_rtc_type = RTC_M4LT81;
swarm_rtc_type = RTC_M41T81;
#ifdef CONFIG_VT
screen_info = (struct screen_info) {

10
arch/mn10300/kernel/time.c
View File

@ -40,21 +40,17 @@ unsigned long long sched_clock(void)
unsigned long long ll;
unsigned l[2];
} tsc64, result;
unsigned long tsc, tmp;
unsigned long tmp;
unsigned product[3]; /* 96-bit intermediate value */
/* cnt32_to_63() is not safe with preemption */
preempt_disable();
/* read the TSC value
*/
tsc = get_cycles();
/* expand to 64-bits.
/* expand the tsc to 64-bits.
* - sched_clock() must be called once a minute or better or the
* following will go horribly wrong - see cnt32_to_63()
*/
tsc64.ll = cnt32_to_63(tsc) & 0x7fffffffffffffffULL;
tsc64.ll = cnt32_to_63(get_cycles()) & 0x7fffffffffffffffULL;
preempt_enable();

2
arch/tile/include/asm/signal.h
View File

@ -25,7 +25,7 @@
#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
struct pt_regs;
int restore_sigcontext(struct pt_regs *, struct sigcontext __user *, long *);
int restore_sigcontext(struct pt_regs *, struct sigcontext __user *);
int setup_sigcontext(struct sigcontext __user *, struct pt_regs *);
void do_signal(struct pt_regs *regs);
#endif

6
arch/tile/kernel/compat_signal.c
View File

@ -290,12 +290,12 @@ long compat_sys_sigaltstack(const struct compat_sigaltstack __user *uss_ptr,
return ret;
}
/* The assembly shim for this function arranges to ignore the return value. */
long compat_sys_rt_sigreturn(struct pt_regs *regs)
{
struct compat_rt_sigframe __user *frame =
(struct compat_rt_sigframe __user *) compat_ptr(regs->sp);
sigset_t set;
long r0;
if (!access_ok(VERIFY_READ, frame, sizeof(*frame)))
goto badframe;
@ -308,13 +308,13 @@ long compat_sys_rt_sigreturn(struct pt_regs *regs)
recalc_sigpending();
spin_unlock_irq(&current->sighand->siglock);
if (restore_sigcontext(regs, &frame->uc.uc_mcontext, &r0))
if (restore_sigcontext(regs, &frame->uc.uc_mcontext))
goto badframe;
if (compat_sys_sigaltstack(&frame->uc.uc_stack, NULL, regs) != 0)
goto badframe;
return r0;
return 0;
badframe:
force_sig(SIGSEGV, current);

24
arch/tile/kernel/intvec_32.S
View File

@ -1342,8 +1342,8 @@ handle_syscall:
lw r20, r20
/* Jump to syscall handler. */
jalr r20; .Lhandle_syscall_link:
FEEDBACK_REENTER(handle_syscall)
jalr r20
.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
/*
* Write our r0 onto the stack so it gets restored instead
@ -1352,6 +1352,9 @@ handle_syscall:
PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
sw r29, r0
.Lsyscall_sigreturn_skip:
FEEDBACK_REENTER(handle_syscall)
/* Do syscall trace again, if requested. */
lw r30, r31
andi r30, r30, _TIF_SYSCALL_TRACE
@ -1536,9 +1539,24 @@ STD_ENTRY_LOCAL(bad_intr)
}; \
STD_ENDPROC(_##x)
/*
* Special-case sigreturn to not write r0 to the stack on return.
* This is technically more efficient, but it also avoids difficulties
* in the 64-bit OS when handling 32-bit compat code, since we must not
* sign-extend r0 for the sigreturn return-value case.
*/
#define PTREGS_SYSCALL_SIGRETURN(x, reg) \
STD_ENTRY(_##x); \
addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
{ \
PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
j x \
}; \
STD_ENDPROC(_##x)
PTREGS_SYSCALL(sys_execve, r3)
PTREGS_SYSCALL(sys_sigaltstack, r2)
PTREGS_SYSCALL(sys_rt_sigreturn, r0)
PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
PTREGS_SYSCALL(sys_cmpxchg_badaddr, r1)
/* Save additional callee-saves to pt_regs, put address in r4 and jump. */

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