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ARM: 9057/1: cache-v7: add missing ISB after cache level selection 

A write to CSSELR needs to complete before its results can be observed
via CCSIDR. So add a ISB to ensure that this is the case.

Acked-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
This commit is contained in:
Ard Biesheuvel 2021-02-11 09:19:46 +01:00 committed by Russell King
parent c4e792d1ac
commit c0e50736e8
1 changed files with 4 additions and 3 deletions
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7
arch/arm/mm/cache-v7.S
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@ -38,9 +38,10 @@ icache_size:
* procedures. * procedures.
*/ */
ENTRY(v7_invalidate_l1) ENTRY(v7_invalidate_l1)
mov r0, #0 mov r0, #0
mcr p15, 2, r0, c0, c0, 0 mcr p15, 2, r0, c0, c0, 0 @ select L1 data cache in CSSELR
mrc p15, 1, r0, c0, c0, 0 isb
mrc p15, 1, r0, c0, c0, 0 @ read cache geometry from CCSIDR
movw r1, #0x7fff movw r1, #0x7fff
and r2, r1, r0, lsr #13 and r2, r1, r0, lsr #13