One fix for the Allwinner A10 SoC's audio PLL that wasn't properly set
and generating noise. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlvGTJIRHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSWO3g//Z5Pjor/691wSROxA7W6TnVJmYfgFthnJ xFuzIY2vXYNng+SH46nSKyjowiFUnXfivEq97AaCMXiFMfYoClvnGjs8NO3IzHMv l2HCuaJSiWBIQSablxErwVFkWvHif/slUWcFmSF3TnyZjmqqOZmYMi3qPya4DOmz exssI0vKiBmkXbi1iwdZKSp1oBvYXZWrxiB/lbxnaDdFC31jSD9a5I0dLEb1vX4j rMMvj+0+FAOofL+u03Q13Ttk1rCkSERE9S0i5rz40z866PlFHxUTJ25njkOJqkmo bARx+MgeS4fFnckcX3p3NSjwhlwr9Yd4+Idt7Y+sCNAYAhSv23I2XShGnAjBJI41 dYpqWuwpWWLnKrsb6gylBXiIVOTsoFvAAbZLlLnyOy+oDDZVDRMvt36JkuYqpYFR kCFzF301JBLEquSjor4Bhprc8i/QmZQWqA5fxe3C+rO8sXBpakKJwjYc5DVhyhma 2h3jPWrCc1QWlC2KHvrKrhwIrsWs+VE7LfQ9IOHMpAy07kxR/7M+AcbDzF68y7iR Mz7fDc/VBiVHL0GNXUNP9KTe7S7uldTf8O8c48inX5GAFGEf8hxNhtcjTkGl2Z8x fegDnXT8YBTHLP8OEMJCQT4euM1P2F9buuCT51QGCzazZwKNXJMRMZEEyfRDk6jO 44q4xK8oQ6A= =Vt/u -----END PGP SIGNATURE----- Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Stephen writes: "clk fixes for v4.19-rc8 One fix for the Allwinner A10 SoC's audio PLL that wasn't properly set and generating noise." * tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: sunxi-ng: sun4i: Set VCO and PLL bias current to lowest setting
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@ -1434,8 +1434,16 @@ static void __init sun4i_ccu_init(struct device_node *node,
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return;
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}
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/* Force the PLL-Audio-1x divider to 1 */
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val = readl(reg + SUN4I_PLL_AUDIO_REG);
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/*
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* Force VCO and PLL bias current to lowest setting. Higher
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* settings interfere with sigma-delta modulation and result
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* in audible noise and distortions when using SPDIF or I2S.
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*/
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val &= ~GENMASK(25, 16);
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/* Force the PLL-Audio-1x divider to 1 */
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val &= ~GENMASK(29, 26);
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writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);
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