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arm64: head: factor out TTBR1 assignment into a macro 

Create a macro load_ttbr1 to avoid having to repeat the same instruction
sequence 3 times in a subsequent patch. No functional change intended.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Link: https://lore.kernel.org/r/20220624150651.1358849-17-ardb@kernel.org
Signed-off-by: Will Deacon <will@kernel.org>
This commit is contained in:
Ard Biesheuvel 2022-06-24 17:06:46 +02:00 committed by Will Deacon
parent a004393f45
commit c0be8f18a3
2 changed files with 14 additions and 8 deletions
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17
arch/arm64/include/asm/assembler.h
View File

@ -479,6 +479,18 @@ alternative_endif
_cond_extable .Licache_op\@, \fixup _cond_extable .Licache_op\@, \fixup
.endm .endm
/*
* load_ttbr1 - install @pgtbl as a TTBR1 page table
* pgtbl preserved
* tmp1/tmp2 clobbered, either may overlap with pgtbl
*/
.macro load_ttbr1, pgtbl, tmp1, tmp2
phys_to_ttbr \tmp1, \pgtbl
offset_ttbr1 \tmp1, \tmp2
msr ttbr1_el1, \tmp1
isb
.endm
/* /*
* To prevent the possibility of old and new partial table walks being visible * To prevent the possibility of old and new partial table walks being visible
* in the tlb, switch the ttbr to a zero page when we invalidate the old * in the tlb, switch the ttbr to a zero page when we invalidate the old
@ -492,10 +504,7 @@ alternative_endif
isb isb
tlbi vmalle1 tlbi vmalle1
dsb nsh dsb nsh
phys_to_ttbr \tmp, \page_table load_ttbr1 \page_table, \tmp, \tmp2
offset_ttbr1 \tmp, \tmp2
msr ttbr1_el1, \tmp
isb
.endm .endm
/* /*

5
arch/arm64/kernel/head.S
View File

@ -722,12 +722,9 @@ SYM_FUNC_START(__enable_mmu)
cmp x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX cmp x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX
b.gt __no_granule_support b.gt __no_granule_support
update_early_cpu_boot_status 0, x3, x4 update_early_cpu_boot_status 0, x3, x4
phys_to_ttbr x1, x1
phys_to_ttbr x2, x2 phys_to_ttbr x2, x2
msr ttbr0_el1, x2 // load TTBR0 msr ttbr0_el1, x2 // load TTBR0
offset_ttbr1 x1, x3 load_ttbr1 x1, x1, x3
msr ttbr1_el1, x1 // load TTBR1
isb
set_sctlr_el1 x0 set_sctlr_el1 x0