UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

Various cleanups for the msm targets. Most of this is removing dead 

code, along with a fix of a sparse warning, a list fix from a semantic
 patch, and marking some functions as static.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.19 (GNU/Linux)
 
 iQIcBAABAgAGBQJQUiYkAAoJEOa6n1xeVN+CgrQQAJACZY7o4IISEHUrE8kqnMh7
 Cb1m/blglnUgXzWhAUwu6FeJhEMeufpaBTGT/hFs95IzAyGqLW3oY1+MmHgGgBMt
 UCaR3fs7prXWfqw0Bvh6hQQ4G/a6tfz0K/CEmJiPcXnI3JleB0c+aItiSuj/jUbA
 R4uReG7mZZsX/iBS70O0cf0ozEc6wdZo2Rys3Snzs7xRMnNhTFPher/Ae/ZxexNp
 Dd7Rly4Ae4VJ1DGN8Eqpl7FKTc7CtTB29AsQJ0dU9vx+34lKsaz/5Aai6LAjqrSn
 xne3cCBuj2Vneix8GNaFw2ApmI9dDlXiGfWhaTy1DieYrQN3ese/zEOIN8qPVIhj
 632Vc1UNmqv3z8YxZhB561lv10y/qMk1P5ZRhiRyyE3Nx5oqv3YANWHXRUmT0YEl
 PkqObZqjGJKoCFR9F5aQrurAbJ26cl7z4YhfuB3EwIPgO0EA87sVn7vF6SvyQ7gK
 0X8dmpj6hkCZxDokJEQckm7iy3kqXGPQ5RfQy3n4MxJstLHu5fHByNlJoATT5ERU
 Pi/djCI1j0Bp/RNHpCMYFyDApTIzlkZIgTXLsYKJqwculYJ5eN/sxkSZWmWqhgdA
 I1T8yhUutukSd5xn0THVPtdhNrTPzF/aHtBauHbAN8LpEQxY8pdpO9Kqn2YU0wRR
 khmjxwZWLkoZ3BoH3sEN
 =Eubw
 -----END PGP SIGNATURE-----

Merge tag 'msm-cleanup-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm into next/cleanup

From David Brown:

Various cleanups for the msm targets.  Most of this is removing dead
code, along with a fix of a sparse warning, a list fix from a semantic
patch, and marking some functions as static.

* tag 'msm-cleanup-for-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/davidb/linux-msm:
  ARM: msm: Remove uncompiled board-msm7x27
  ARM: msm: Remove unused acpuclock-arm11
  ARM: msm: dma: use list_move_tail instead of list_del/list_add_tail
  ARM: msm: Fix sparse warnings due to incorrect type
  ARM: msm: Remove unused idle.c
  ARM: msm: clock-pcom: Mark functions static
  ARM: msm: Remove msm_hw_reset_hook
This commit is contained in:
Olof Johansson 2012-09-16 17:45:45 -07:00
parent d0312d7edc e63770acb3
commit c098c9f2aa
15 changed files with 14 additions and 831 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/mach-msm/Makefile
View File

@ -1,11 +1,11 @@
obj-y += io.o idle.o timer.o
obj-y += io.o timer.o
obj-y += clock.o
obj-$(CONFIG_DEBUG_FS) += clock-debug.o
obj-$(CONFIG_MSM_VIC) += irq-vic.o
obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
obj-$(CONFIG_ARCH_MSM7X30) += dma.o
obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o

525
arch/arm/mach-msm/acpuclock-arm11.c
View File

@ -1,525 +0,0 @@
/* arch/arm/mach-msm/acpuclock.c
*
* MSM architecture clock driver
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2007 QUALCOMM Incorporated
* Author: San Mehat <san@android.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/errno.h>
#include <linux/string.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/cpufreq.h>
#include <linux/mutex.h>
#include <linux/io.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include "proc_comm.h"
#include "acpuclock.h"
#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
/*
* ARM11 clock configuration for specific ACPU speeds
*/
#define ACPU_PLL_TCXO -1
#define ACPU_PLL_0 0
#define ACPU_PLL_1 1
#define ACPU_PLL_2 2
#define ACPU_PLL_3 3
#define PERF_SWITCH_DEBUG 0
#define PERF_SWITCH_STEP_DEBUG 0
struct clock_state
{
struct clkctl_acpu_speed *current_speed;
struct mutex lock;
uint32_t acpu_switch_time_us;
uint32_t max_speed_delta_khz;
uint32_t vdd_switch_time_us;
unsigned long power_collapse_khz;
unsigned long wait_for_irq_khz;
};
static struct clk *ebi1_clk;
static struct clock_state drv_state = { 0 };
static void __init acpuclk_init(void);
/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
enum {
VDD_0 = 0,
VDD_1 = 1,
VDD_2 = 2,
VDD_3 = 3,
VDD_4 = 3,
VDD_5 = 3,
VDD_6 = 3,
VDD_7 = 7,
VDD_END
};
struct clkctl_acpu_speed {
unsigned int a11clk_khz;
int pll;
unsigned int a11clk_src_sel;
unsigned int a11clk_src_div;
unsigned int ahbclk_khz;
unsigned int ahbclk_div;
int vdd;
unsigned int axiclk_khz;
unsigned long lpj; /* loops_per_jiffy */
/* Index in acpu_freq_tbl[] for steppings. */
short down;
short up;
};
/*
* ACPU speed table. Complete table is shown but certain speeds are commented
* out to optimized speed switching. Initialize loops_per_jiffy to 0.
*
* Table stepping up/down is optimized for 256mhz jumps while staying on the
* same PLL.
*/
#if (0)
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
{ 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 },
{ 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 },
{ 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 },
{ 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 },
{ 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 },
{ 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 },
{ 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 },
{ 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 },
{ 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
{ 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 },
{ 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 },
{ 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
{ 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
};
#else /* Table of freq we currently use. */
static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
{ 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
{ 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
{ 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
{ 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
{ 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
{ 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
{ 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
};
#endif
#ifdef CONFIG_CPU_FREQ_TABLE
static struct cpufreq_frequency_table freq_table[] = {
{ 0, 122880 },
{ 1, 128000 },
{ 2, 245760 },
{ 3, 384000 },
{ 4, 528000 },
{ 5, CPUFREQ_TABLE_END },
};
#endif
static int pc_pll_request(unsigned id, unsigned on)
{
int res;
on = !!on;
#if PERF_SWITCH_DEBUG
if (on)
printk(KERN_DEBUG "Enabling PLL %d\n", id);
else
printk(KERN_DEBUG "Disabling PLL %d\n", id);
#endif
res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
if (res < 0)
return res;
#if PERF_SWITCH_DEBUG
if (on)
printk(KERN_DEBUG "PLL %d enabled\n", id);
else
printk(KERN_DEBUG "PLL %d disabled\n", id);
#endif
return res;
}
/*----------------------------------------------------------------------------
* ARM11 'owned' clock control
*---------------------------------------------------------------------------*/
unsigned long acpuclk_power_collapse(void) {
int ret = acpuclk_get_rate();
ret *= 1000;
if (ret > drv_state.power_collapse_khz)
acpuclk_set_rate(drv_state.power_collapse_khz, 1);
return ret;
}
unsigned long acpuclk_get_wfi_rate(void)
{
return drv_state.wait_for_irq_khz;
}
unsigned long acpuclk_wait_for_irq(void) {
int ret = acpuclk_get_rate();
ret *= 1000;
if (ret > drv_state.wait_for_irq_khz)
acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
return ret;
}
static int acpuclk_set_vdd_level(int vdd)
{
uint32_t current_vdd;
current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
#if PERF_SWITCH_DEBUG
printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
current_vdd, vdd);
#endif
writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
udelay(drv_state.vdd_switch_time_us);
if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
#if PERF_SWITCH_DEBUG
printk(KERN_ERR "acpuclock: VDD set failed\n");
#endif
return -EIO;
}
#if PERF_SWITCH_DEBUG
printk(KERN_DEBUG "acpuclock: VDD switched\n");
#endif
return 0;
}
/* Set proper dividers for the given clock speed. */
static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
uint32_t reg_clkctl, reg_clksel, clk_div;
/* AHB_CLK_DIV */
clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
/*
* If the new clock divider is higher than the previous, then
* program the divider before switching the clock
*/
if (hunt_s->ahbclk_div > clk_div) {
reg_clksel = readl(A11S_CLK_SEL_ADDR);
reg_clksel &= ~(0x3 << 1);
reg_clksel |= (hunt_s->ahbclk_div << 1);
writel(reg_clksel, A11S_CLK_SEL_ADDR);
}
if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
/* SRC0 */
/* Program clock source */
reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
reg_clkctl &= ~(0x07 << 4);
reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
/* Program clock divider */
reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
reg_clkctl &= ~0xf;
reg_clkctl |= hunt_s->a11clk_src_div;
writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
/* Program clock source selection */
reg_clksel = readl(A11S_CLK_SEL_ADDR);
reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */
writel(reg_clksel, A11S_CLK_SEL_ADDR);
} else {
/* SRC1 */
/* Program clock source */
reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
reg_clkctl &= ~(0x07 << 12);
reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
/* Program clock divider */
reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
reg_clkctl &= ~(0xf << 8);
reg_clkctl |= (hunt_s->a11clk_src_div << 8);
writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
/* Program clock source selection */
reg_clksel = readl(A11S_CLK_SEL_ADDR);
reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */
writel(reg_clksel, A11S_CLK_SEL_ADDR);
}
/*
* If the new clock divider is lower than the previous, then
* program the divider after switching the clock
*/
if (hunt_s->ahbclk_div < clk_div) {
reg_clksel = readl(A11S_CLK_SEL_ADDR);
reg_clksel &= ~(0x3 << 1);
reg_clksel |= (hunt_s->ahbclk_div << 1);
writel(reg_clksel, A11S_CLK_SEL_ADDR);
}
}
int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
{
uint32_t reg_clkctl;
struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
int rc = 0;
unsigned int plls_enabled = 0, pll;
strt_s = cur_s = drv_state.current_speed;
WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
if (cur_s == NULL)
return -ENOENT;
if (rate == (cur_s->a11clk_khz * 1000))
return 0;
for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
if (tgt_s->a11clk_khz == (rate / 1000))
break;
}
if (tgt_s->a11clk_khz == 0)
return -EINVAL;
/* Choose the highest speed speed at or below 'rate' with same PLL. */
if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
tgt_s--;
}
if (strt_s->pll != ACPU_PLL_TCXO)
plls_enabled |= 1 << strt_s->pll;
if (!for_power_collapse) {
mutex_lock(&drv_state.lock);
if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
rc = pc_pll_request(tgt_s->pll, 1);
if (rc < 0) {
pr_err("PLL%d enable failed (%d)\n",
tgt_s->pll, rc);
goto out;
}
plls_enabled |= 1 << tgt_s->pll;
}
/* Increase VDD if needed. */
if (tgt_s->vdd > cur_s->vdd) {
if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
printk(KERN_ERR "Unable to switch ACPU vdd\n");
goto out;
}
}
}
/* Set wait states for CPU between frequency changes */
reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
#if PERF_SWITCH_DEBUG
printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
#endif
while (cur_s != tgt_s) {
/*
* Always jump to target freq if within 256mhz, regulardless of
* PLL. If differnece is greater, use the predefinied
* steppings in the table.
*/
int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
if (d > drv_state.max_speed_delta_khz) {
/* Step up or down depending on target vs current. */
int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
cur_s->up : cur_s->down;
if (clk_index < 0) { /* This should not happen. */
printk(KERN_ERR "cur:%u target: %u\n",
cur_s->a11clk_khz, tgt_s->a11clk_khz);
rc = -EINVAL;
goto out;
}
cur_s = &acpu_freq_tbl[clk_index];
} else {
cur_s = tgt_s;
}
#if PERF_SWITCH_STEP_DEBUG
printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
__FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
#endif
if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
&& !(plls_enabled & (1 << cur_s->pll))) {
rc = pc_pll_request(cur_s->pll, 1);
if (rc < 0) {
pr_err("PLL%d enable failed (%d)\n",
cur_s->pll, rc);
goto out;
}
plls_enabled |= 1 << cur_s->pll;
}
acpuclk_set_div(cur_s);
drv_state.current_speed = cur_s;
/* Re-adjust lpj for the new clock speed. */
loops_per_jiffy = cur_s->lpj;
udelay(drv_state.acpu_switch_time_us);
}
/* Nothing else to do for power collapse. */
if (for_power_collapse)
return 0;
/* Disable PLLs we are not using anymore. */
plls_enabled &= ~(1 << tgt_s->pll);
for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
if (plls_enabled & (1 << pll)) {
rc = pc_pll_request(pll, 0);
if (rc < 0) {
pr_err("PLL%d disable failed (%d)\n", pll, rc);
goto out;
}
}
/* Change the AXI bus frequency if we can. */
if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
if (rc < 0)
pr_err("Setting AXI min rate failed!\n");
}
/* Drop VDD level if we can. */
if (tgt_s->vdd < strt_s->vdd) {
if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
}
#if PERF_SWITCH_DEBUG
printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
#endif
out:
if (!for_power_collapse)
mutex_unlock(&drv_state.lock);
return rc;
}
static void __init acpuclk_init(void)
{
struct clkctl_acpu_speed *speed;
uint32_t div, sel;
int rc;
/*
* Determine the rate of ACPU clock
*/
if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
/* CLK_SRC0_SEL */
sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
/* CLK_SRC0_DIV */
div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
} else {
/* CLK_SRC1_SEL */
sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
/* CLK_SRC1_DIV */
div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
}
for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
if (speed->a11clk_src_sel == sel
&& (speed->a11clk_src_div == div))
break;
}
if (speed->a11clk_khz == 0) {
printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
return;
}
drv_state.current_speed = speed;
rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
if (rc < 0)
pr_err("Setting AXI min rate failed!\n");
printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
}
unsigned long acpuclk_get_rate(void)
{
WARN_ONCE(drv_state.current_speed == NULL,
"acpuclk_get_rate: not initialized\n");
if (drv_state.current_speed)
return drv_state.current_speed->a11clk_khz;
else
return 0;
}
uint32_t acpuclk_get_switch_time(void)
{
return drv_state.acpu_switch_time_us;
}
/*----------------------------------------------------------------------------
* Clock driver initialization
*---------------------------------------------------------------------------*/
/* Initialize the lpj field in the acpu_freq_tbl. */
static void __init lpj_init(void)
{
int i;
const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
base_clk->a11clk_khz,
acpu_freq_tbl[i].a11clk_khz);
}
}
void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
{
pr_info("acpu_clock_init()\n");
ebi1_clk = clk_get(NULL, "ebi1_clk");
mutex_init(&drv_state.lock);
drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
drv_state.power_collapse_khz = clkdata->power_collapse_khz;
drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
acpuclk_init();
lpj_init();
#ifdef CONFIG_CPU_FREQ_TABLE
cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
#endif
}

32
arch/arm/mach-msm/acpuclock.h
View File

@ -1,32 +0,0 @@
/* arch/arm/mach-msm/acpuclock.h
*
* MSM architecture clock driver header
*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2007 QUALCOMM Incorporated
* Author: San Mehat <san@android.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
unsigned long acpuclk_get_rate(void);
uint32_t acpuclk_get_switch_time(void);
unsigned long acpuclk_wait_for_irq(void);
unsigned long acpuclk_power_collapse(void);
unsigned long acpuclk_get_wfi_rate(void);
#endif

1
arch/arm/mach-msm/board-mahimahi.c
View File

@ -30,7 +30,6 @@
#include <mach/board.h>
#include <mach/hardware.h>
#include <mach/system.h>
#include "board-mahimahi.h"
#include "devices.h"

170
arch/arm/mach-msm/board-msm7x27.c
View File

@ -1,170 +0,0 @@
/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/gpio.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/input.h>
#include <linux/io.h>
#include <linux/delay.h>
#include <linux/power_supply.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <asm/setup.h>
#ifdef CONFIG_CACHE_L2X0
#include <asm/hardware/cache-l2x0.h>
#endif
#include <mach/vreg.h>
#include <mach/mpp.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include "devices.h"
#include "socinfo.h"
#include "clock.h"
static struct resource smc91x_resources[] = {
[0] = {
.start = 0x9C004300,
.end = 0x9C0043ff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = MSM_GPIO_TO_INT(132),
.end = MSM_GPIO_TO_INT(132),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static struct platform_device *devices[] __initdata = {
&msm_device_uart3,
&msm_device_smd,
&msm_device_dmov,
&msm_device_nand,
&smc91x_device,
};
extern struct sys_timer msm_timer;
static void __init msm7x2x_init_irq(void)
{
msm_init_irq();
}
static void __init msm7x2x_init(void)
{
if (socinfo_init() < 0)
BUG();
if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) {
smc91x_resources[0].start = 0x98000300;
smc91x_resources[0].end = 0x980003ff;
smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
if (gpio_tlmm_config(GPIO_CFG(85, 0,
GPIO_INPUT,
GPIO_PULL_DOWN,
GPIO_2MA),
GPIO_ENABLE)) {
printk(KERN_ERR
"%s: Err: Config GPIO-85 INT\n",
__func__);
}
}
platform_add_devices(devices, ARRAY_SIZE(devices));
}
static void __init msm7x2x_map_io(void)
{
msm_map_common_io();
/* Technically dependent on the SoC but using machine_is
* macros since socinfo is not available this early and there
* are plans to restructure the code which will eliminate the
* need for socinfo.
*/
if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa())
msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27);
if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa())
msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
#ifdef CONFIG_CACHE_L2X0
if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) {
/* 7x27 has 256KB L2 cache:
64Kb/Way and 4-Way Associativity;
R/W latency: 3 cycles;
evmon/parity/share disabled. */
l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
}
#endif
}
static void __init msm7x2x_init_late(void)
{
smd_debugfs_init();
}
MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
.atag_offset = 0x100,
.map_io = msm7x2x_map_io,
.init_irq = msm7x2x_init_irq,
.init_machine = msm7x2x_init,
.init_late = msm7x2x_init_late,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
.atag_offset = 0x100,
.map_io = msm7x2x_map_io,
.init_irq = msm7x2x_init_irq,
.init_machine = msm7x2x_init,
.init_late = msm7x2x_init_late,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
.atag_offset = 0x100,
.map_io = msm7x2x_map_io,
.init_irq = msm7x2x_init_irq,
.init_machine = msm7x2x_init,
.init_late = msm7x2x_init_late,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
.atag_offset = 0x100,
.map_io = msm7x2x_map_io,
.init_irq = msm7x2x_init_irq,
.init_machine = msm7x2x_init,
.init_late = msm7x2x_init_late,
.timer = &msm_timer,
MACHINE_END

1
arch/arm/mach-msm/board-sapphire.c
View File

@ -27,7 +27,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
#include <mach/system.h>
#include <mach/vreg.h>
#include <mach/board.h>

18
arch/arm/mach-msm/clock-pcom.c
View File

@ -25,7 +25,7 @@
/*
* glue for the proc_comm interface
*/
int pc_clk_enable(unsigned id)
static int pc_clk_enable(unsigned id)
{
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
if (rc < 0)
@ -34,7 +34,7 @@ int pc_clk_enable(unsigned id)
return (int)id < 0 ? -EINVAL : 0;
}
void pc_clk_disable(unsigned id)
static void pc_clk_disable(unsigned id)
{
msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
}
@ -54,7 +54,7 @@ int pc_clk_reset(unsigned id, enum clk_reset_action action)
return (int)id < 0 ? -EINVAL : 0;
}
int pc_clk_set_rate(unsigned id, unsigned rate)
static int pc_clk_set_rate(unsigned id, unsigned rate)
{
/* The rate _might_ be rounded off to the nearest KHz value by the
* remote function. So a return value of 0 doesn't necessarily mean
@ -67,7 +67,7 @@ int pc_clk_set_rate(unsigned id, unsigned rate)
return (int)id < 0 ? -EINVAL : 0;
}
int pc_clk_set_min_rate(unsigned id, unsigned rate)
static int pc_clk_set_min_rate(unsigned id, unsigned rate)
{
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
if (rc < 0)
@ -76,7 +76,7 @@ int pc_clk_set_min_rate(unsigned id, unsigned rate)
return (int)id < 0 ? -EINVAL : 0;
}
int pc_clk_set_max_rate(unsigned id, unsigned rate)
static int pc_clk_set_max_rate(unsigned id, unsigned rate)
{
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
if (rc < 0)
@ -85,7 +85,7 @@ int pc_clk_set_max_rate(unsigned id, unsigned rate)
return (int)id < 0 ? -EINVAL : 0;
}
int pc_clk_set_flags(unsigned id, unsigned flags)
static int pc_clk_set_flags(unsigned id, unsigned flags)
{
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
if (rc < 0)
@ -94,7 +94,7 @@ int pc_clk_set_flags(unsigned id, unsigned flags)
return (int)id < 0 ? -EINVAL : 0;
}
unsigned pc_clk_get_rate(unsigned id)
static unsigned pc_clk_get_rate(unsigned id)
{
if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
return 0;
@ -102,7 +102,7 @@ unsigned pc_clk_get_rate(unsigned id)
return id;
}
unsigned pc_clk_is_enabled(unsigned id)
static unsigned pc_clk_is_enabled(unsigned id)
{
if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
return 0;
@ -110,7 +110,7 @@ unsigned pc_clk_is_enabled(unsigned id)
return id;
}
long pc_clk_round_rate(unsigned id, unsigned rate)
static long pc_clk_round_rate(unsigned id, unsigned rate)
{
/* Not really supported; pc_clk_set_rate() does rounding on it's own. */

3
arch/arm/mach-msm/dma.c
View File

@ -223,8 +223,7 @@ static irqreturn_t msm_datamover_irq_handler(int irq, void *dev_id)
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
list_del(&cmd->list);
list_add_tail(&cmd->list, &active_commands[id]);
list_move_tail(&cmd->list, &active_commands[id]);
if (cmd->execute_func)
cmd->execute_func(cmd);
PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);

49
arch/arm/mach-msm/idle.c
View File

@ -1,49 +0,0 @@
/* arch/arm/mach-msm/idle.c
*
* Idle processing for MSM7K - work around bugs with SWFI.
*
* Copyright (c) 2007 QUALCOMM Incorporated.
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <asm/system.h>
static void msm_idle(void)
{
#ifdef CONFIG_MSM7X00A_IDLE
asm volatile (
"mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t"
"bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t"
"bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t"
"mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t"
"mov r0, #0 /* prepare wfi value */ \n\t"
"mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t"
"mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t"
"mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t"
"mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t"
: : : "r0","r1" );
#endif
}
static int __init msm_idle_init(void)
{
arm_pm_idle = msm_idle;
return 0;
}
arch_initcall(msm_idle_init);

10
arch/arm/mach-msm/include/mach/board.h
View File

@ -22,15 +22,6 @@
/* platform device data structures */
struct msm_acpu_clock_platform_data
{
uint32_t acpu_switch_time_us;
uint32_t max_speed_delta_khz;
uint32_t vdd_switch_time_us;
unsigned long power_collapse_khz;
unsigned long wait_for_irq_khz;
};
struct clk_lookup;
extern struct sys_timer msm_timer;
@ -42,7 +33,6 @@ void __init msm_map_common_io(void);
void __init msm_init_irq(void);
void __init msm_init_gpio(void);
void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
int __init msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags);

19
arch/arm/mach-msm/include/mach/system.h
View File

@ -1,19 +0,0 @@
/* arch/arm/mach-msm/include/mach/system.h
*
* Copyright (C) 2007 Google, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
/* low level hardware reset hook -- for example, hitting the
* PSHOLD line on the PMIC to hard reset the system
*/
extern void (*msm_hw_reset_hook)(void);

3
arch/arm/mach-msm/io.c
View File

@ -38,8 +38,7 @@
#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
|| defined(CONFIG_ARCH_MSM7X25)
#if defined(CONFIG_ARCH_MSM7X00A)
static struct map_desc msm_io_desc[] __initdata = {
MSM_DEVICE(VIC),
MSM_CHIP_DEVICE(CSR, MSM7X00),

1
arch/arm/mach-msm/proc_comm.c
View File

@ -19,7 +19,6 @@
#include <linux/io.h>
#include <linux/spinlock.h>
#include <mach/msm_iomap.h>
#include <mach/system.h>
#include "proc_comm.h"

7
arch/arm/mach-msm/smd.c
View File

@ -30,7 +30,6 @@
#include <linux/delay.h>
#include <mach/msm_smd.h>
#include <mach/system.h>
#include "smd_private.h"
#include "proc_comm.h"
@ -39,8 +38,6 @@
#define CONFIG_QDSP6 1
#endif
void (*msm_hw_reset_hook)(void);
#define MODULE_NAME "msm_smd"
enum {
@ -101,10 +98,6 @@ static void handle_modem_crash(void)
pr_err("ARM9 has CRASHED\n");
smd_diag();
/* hard reboot if possible */
if (msm_hw_reset_hook)
msm_hw_reset_hook();
/* in this case the modem or watchdog should reboot us */
for (;;)
;

2
arch/arm/mach-msm/timer.c
View File

@ -101,7 +101,7 @@ static struct clock_event_device msm_clockevent = {
static union {
struct clock_event_device *evt;
struct clock_event_device __percpu **percpu_evt;
struct clock_event_device * __percpu *percpu_evt;
} msm_evt;
static void __iomem *source_base;