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drm/amd/display: Add missing HBM support and raise Vega20's uclk. 

[Why]
When more than 2 displays are connected to the graphics card,
only the minimum memory clock is needed. However, when more
displays are connected, the minimum memory clock is not
sufficient enough to support the overwhelming bandwidth.
System will hang under this circumstance.

Also, the old code didn't address HBM cards, which has 2
pseudo channels. We need to add the HBM part here.

[How]
When graphics card connects to 2 or more displays,
switch to high memory clock. Also, choose memory
multiplier based on whether its regular DRAM or HBM.

Signed-off-by: Zhan Liu <zhan.liu@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Zhan Liu 2019-08-22 14:54:18 -04:00 committed by Alex Deucher
parent c46e5df4ac
commit c02d6a1613
1 changed files with 16 additions and 2 deletions
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18
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
View File

@ -174,6 +174,10 @@ void dce11_pplib_apply_display_requirements(
struct dc_state *context) struct dc_state *context)
{ {
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ;
if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm)
memory_type_multiplier = MEMORY_TYPE_HBM;
pp_display_cfg->all_displays_in_sync = pp_display_cfg->all_displays_in_sync =
context->bw_ctx.bw.dce.all_displays_in_sync; context->bw_ctx.bw.dce.all_displays_in_sync;
@ -186,8 +190,18 @@ void dce11_pplib_apply_display_requirements(
pp_display_cfg->cpu_pstate_separation_time = pp_display_cfg->cpu_pstate_separation_time =
context->bw_ctx.bw.dce.blackout_recovery_time_us; context->bw_ctx.bw.dce.blackout_recovery_time_us;
pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz /*
/ MEMORY_TYPE_MULTIPLIER_CZ; * TODO: determine whether the bandwidth has reached memory's limitation
* , then change minimum memory clock based on real-time bandwidth
* limitation.
*/
if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) {
pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz,
(uint32_t) (dc->bw_vbios->high_yclk.value / memory_type_multiplier / 10000));
} else {
pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz
/ memory_type_multiplier;
}
pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box(
dc, dc,