ALSA: ice1712: Add Wolfson Microelectronics WM8776 codec support
Needed by Philips PSC724 subdriver. The code does not contain any card-specific bits so other ice17xx cards using this codec could be converted to use this generic code. Signed-off-by: Ondrej Zary <linux@rainbow-software.org> Signed-off-by: Takashi Iwai <tiwai@suse.de>
This commit is contained in:
Ondrej Zary
Takashi Iwai
parent
45d44e5a94
commit
bfe514279c
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@ -0,0 +1,632 @@
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/*
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* ALSA driver for ICEnsemble VT17xx
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*
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* Lowlevel functions for WM8776 codec
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*
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* Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <linux/delay.h>
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#include <sound/core.h>
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#include <sound/control.h>
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#include <sound/tlv.h>
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#include "wm8776.h"
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/* low-level access */
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static void snd_wm8776_write(struct snd_wm8776 *wm, u16 addr, u16 data)
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{
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u8 bus_addr = addr << 1 | data >> 8; /* addr + 9th data bit */
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u8 bus_data = data & 0xff; /* remaining 8 data bits */
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if (addr < WM8776_REG_RESET)
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wm->regs[addr] = data;
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wm->ops.write(wm, bus_addr, bus_data);
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}
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/* register-level functions */
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static void snd_wm8776_activate_ctl(struct snd_wm8776 *wm, char *ctl_name,
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bool active)
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{
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struct snd_card *card = wm->card;
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struct snd_kcontrol *kctl;
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struct snd_kcontrol_volatile *vd;
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struct snd_ctl_elem_id elem_id;
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unsigned int index_offset;
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memset(&elem_id, 0, sizeof(elem_id));
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strncpy(elem_id.name, ctl_name, sizeof(elem_id.name));
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elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
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kctl = snd_ctl_find_id(card, &elem_id);
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if (!kctl)
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return;
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index_offset = snd_ctl_get_ioff(kctl, &kctl->id);
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vd = &kctl->vd[index_offset];
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if (active)
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vd->access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
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else
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vd->access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
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snd_ctl_notify(card, SNDRV_CTL_EVENT_MASK_INFO, &kctl->id);
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}
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static void snd_wm8776_update_agc_ctl(struct snd_wm8776 *wm)
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{
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int i, flags_on = 0, flags_off = 0;
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switch (wm->agc_mode) {
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case WM8776_AGC_OFF:
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flags_off = WM8776_FLAG_LIM | WM8776_FLAG_ALC;
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break;
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case WM8776_AGC_LIM:
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flags_off = WM8776_FLAG_ALC;
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flags_on = WM8776_FLAG_LIM;
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break;
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case WM8776_AGC_ALC_R:
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case WM8776_AGC_ALC_L:
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case WM8776_AGC_ALC_STEREO:
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flags_off = WM8776_FLAG_LIM;
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flags_on = WM8776_FLAG_ALC;
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break;
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}
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for (i = 0; i < WM8776_CTL_COUNT; i++)
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if (wm->ctl[i].flags & flags_off)
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snd_wm8776_activate_ctl(wm, wm->ctl[i].name, false);
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else if (wm->ctl[i].flags & flags_on)
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snd_wm8776_activate_ctl(wm, wm->ctl[i].name, true);
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}
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static void snd_wm8776_set_agc(struct snd_wm8776 *wm, u16 agc, u16 nothing)
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{
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u16 alc1 = wm->regs[WM8776_REG_ALCCTRL1] & ~WM8776_ALC1_LCT_MASK;
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u16 alc2 = wm->regs[WM8776_REG_ALCCTRL2] & ~WM8776_ALC2_LCEN;
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switch (agc) {
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case 0: /* Off */
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wm->agc_mode = WM8776_AGC_OFF;
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break;
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case 1: /* Limiter */
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alc2 |= WM8776_ALC2_LCEN;
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wm->agc_mode = WM8776_AGC_LIM;
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break;
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case 2: /* ALC Right */
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alc1 |= WM8776_ALC1_LCSEL_ALCR;
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alc2 |= WM8776_ALC2_LCEN;
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wm->agc_mode = WM8776_AGC_ALC_R;
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break;
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case 3: /* ALC Left */
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alc1 |= WM8776_ALC1_LCSEL_ALCL;
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alc2 |= WM8776_ALC2_LCEN;
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wm->agc_mode = WM8776_AGC_ALC_L;
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break;
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case 4: /* ALC Stereo */
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alc1 |= WM8776_ALC1_LCSEL_ALCSTEREO;
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alc2 |= WM8776_ALC2_LCEN;
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wm->agc_mode = WM8776_AGC_ALC_STEREO;
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break;
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}
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snd_wm8776_write(wm, WM8776_REG_ALCCTRL1, alc1);
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snd_wm8776_write(wm, WM8776_REG_ALCCTRL2, alc2);
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snd_wm8776_update_agc_ctl(wm);
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}
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static void snd_wm8776_get_agc(struct snd_wm8776 *wm, u16 *mode, u16 *nothing)
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{
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*mode = wm->agc_mode;
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}
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/* mixer controls */
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static const DECLARE_TLV_DB_SCALE(wm8776_hp_tlv, -7400, 100, 1);
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static const DECLARE_TLV_DB_SCALE(wm8776_dac_tlv, -12750, 50, 1);
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static const DECLARE_TLV_DB_SCALE(wm8776_adc_tlv, -10350, 50, 1);
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static const DECLARE_TLV_DB_SCALE(wm8776_lct_tlv, -1600, 100, 0);
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static const DECLARE_TLV_DB_SCALE(wm8776_maxgain_tlv, 0, 400, 0);
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static const DECLARE_TLV_DB_SCALE(wm8776_ngth_tlv, -7800, 600, 0);
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static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_lim_tlv, -1200, 100, 0);
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static const DECLARE_TLV_DB_SCALE(wm8776_maxatten_alc_tlv, -2100, 400, 0);
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static struct snd_wm8776_ctl snd_wm8776_default_ctl[WM8776_CTL_COUNT] = {
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[WM8776_CTL_DAC_VOL] = {
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.name = "Master Playback Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8776_dac_tlv,
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.reg1 = WM8776_REG_DACLVOL,
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.reg2 = WM8776_REG_DACRVOL,
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.mask1 = WM8776_DACVOL_MASK,
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.mask2 = WM8776_DACVOL_MASK,
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.max = 0xff,
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.flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
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},
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[WM8776_CTL_DAC_SW] = {
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.name = "Master Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_DACCTRL1,
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.reg2 = WM8776_REG_DACCTRL1,
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.mask1 = WM8776_DAC_PL_LL,
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.mask2 = WM8776_DAC_PL_RR,
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.flags = WM8776_FLAG_STEREO,
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},
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[WM8776_CTL_DAC_ZC_SW] = {
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.name = "Master Zero Cross Detect Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_DACCTRL1,
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.mask1 = WM8776_DAC_DZCEN,
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},
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[WM8776_CTL_HP_VOL] = {
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.name = "Headphone Playback Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8776_hp_tlv,
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.reg1 = WM8776_REG_HPLVOL,
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.reg2 = WM8776_REG_HPRVOL,
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.mask1 = WM8776_HPVOL_MASK,
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.mask2 = WM8776_HPVOL_MASK,
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.min = 0x2f,
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.max = 0x7f,
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.flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
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},
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[WM8776_CTL_HP_SW] = {
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.name = "Headphone Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_PWRDOWN,
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.mask1 = WM8776_PWR_HPPD,
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.flags = WM8776_FLAG_INVERT,
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},
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[WM8776_CTL_HP_ZC_SW] = {
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.name = "Headphone Zero Cross Detect Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_HPLVOL,
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.reg2 = WM8776_REG_HPRVOL,
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.mask1 = WM8776_VOL_HPZCEN,
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.mask2 = WM8776_VOL_HPZCEN,
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.flags = WM8776_FLAG_STEREO,
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},
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[WM8776_CTL_AUX_SW] = {
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.name = "AUX Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_OUTMUX,
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.mask1 = WM8776_OUTMUX_AUX,
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},
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[WM8776_CTL_BYPASS_SW] = {
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.name = "Bypass Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_OUTMUX,
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.mask1 = WM8776_OUTMUX_BYPASS,
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},
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[WM8776_CTL_DAC_IZD_SW] = {
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.name = "Infinite Zero Detect Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_DACCTRL1,
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.mask1 = WM8776_DAC_IZD,
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},
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[WM8776_CTL_PHASE_SW] = {
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.name = "Phase Invert Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_PHASESWAP,
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.reg2 = WM8776_REG_PHASESWAP,
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.mask1 = WM8776_PHASE_INVERTL,
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.mask2 = WM8776_PHASE_INVERTR,
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.flags = WM8776_FLAG_STEREO,
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},
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[WM8776_CTL_DEEMPH_SW] = {
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.name = "Deemphasis Playback Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_DACCTRL2,
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.mask1 = WM8776_DAC2_DEEMPH,
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},
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[WM8776_CTL_ADC_VOL] = {
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.name = "Input Capture Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8776_adc_tlv,
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.reg1 = WM8776_REG_ADCLVOL,
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.reg2 = WM8776_REG_ADCRVOL,
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.mask1 = WM8776_ADC_GAIN_MASK,
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.mask2 = WM8776_ADC_GAIN_MASK,
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.max = 0xff,
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.flags = WM8776_FLAG_STEREO | WM8776_FLAG_VOL_UPDATE,
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},
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[WM8776_CTL_ADC_SW] = {
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.name = "Input Capture Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_ADCMUX,
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.reg2 = WM8776_REG_ADCMUX,
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.mask1 = WM8776_ADC_MUTEL,
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.mask2 = WM8776_ADC_MUTER,
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.flags = WM8776_FLAG_STEREO | WM8776_FLAG_INVERT,
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},
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[WM8776_CTL_INPUT1_SW] = {
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.name = "AIN1 Capture Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_ADCMUX,
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.mask1 = WM8776_ADC_MUX_AIN1,
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},
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[WM8776_CTL_INPUT2_SW] = {
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.name = "AIN2 Capture Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_ADCMUX,
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.mask1 = WM8776_ADC_MUX_AIN2,
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},
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[WM8776_CTL_INPUT3_SW] = {
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.name = "AIN3 Capture Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_ADCMUX,
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.mask1 = WM8776_ADC_MUX_AIN3,
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},
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[WM8776_CTL_INPUT4_SW] = {
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.name = "AIN4 Capture Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_ADCMUX,
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.mask1 = WM8776_ADC_MUX_AIN4,
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},
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[WM8776_CTL_INPUT5_SW] = {
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.name = "AIN5 Capture Switch",
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.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
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.reg1 = WM8776_REG_ADCMUX,
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.mask1 = WM8776_ADC_MUX_AIN5,
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},
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[WM8776_CTL_AGC_SEL] = {
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.name = "AGC Select Capture Enum",
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.type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
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.enum_names = { "Off", "Limiter", "ALC Right", "ALC Left",
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"ALC Stereo" },
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.max = 5, /* .enum_names item count */
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.set = snd_wm8776_set_agc,
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.get = snd_wm8776_get_agc,
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},
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[WM8776_CTL_LIM_THR] = {
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.name = "Limiter Threshold Capture Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8776_lct_tlv,
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.reg1 = WM8776_REG_ALCCTRL1,
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.mask1 = WM8776_ALC1_LCT_MASK,
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.max = 15,
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.flags = WM8776_FLAG_LIM,
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},
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[WM8776_CTL_LIM_ATK] = {
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.name = "Limiter Attack Time Capture Enum",
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.type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
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.enum_names = { "0.25 ms", "0.5 ms", "1 ms", "2 ms", "4 ms",
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"8 ms", "16 ms", "32 ms", "64 ms", "128 ms", "256 ms" },
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.max = 11, /* .enum_names item count */
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.reg1 = WM8776_REG_ALCCTRL3,
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.mask1 = WM8776_ALC3_ATK_MASK,
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.flags = WM8776_FLAG_LIM,
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},
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[WM8776_CTL_LIM_DCY] = {
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.name = "Limiter Decay Time Capture Enum",
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.type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
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.enum_names = { "1.2 ms", "2.4 ms", "4.8 ms", "9.6 ms",
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"19.2 ms", "38.4 ms", "76.8 ms", "154 ms", "307 ms",
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"614 ms", "1.23 s" },
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.max = 11, /* .enum_names item count */
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.reg1 = WM8776_REG_ALCCTRL3,
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.mask1 = WM8776_ALC3_DCY_MASK,
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.flags = WM8776_FLAG_LIM,
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},
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[WM8776_CTL_LIM_TRANWIN] = {
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.name = "Limiter Transient Window Capture Enum",
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.type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
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.enum_names = { "0 us", "62.5 us", "125 us", "250 us", "500 us",
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"1 ms", "2 ms", "4 ms" },
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.max = 8, /* .enum_names item count */
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.reg1 = WM8776_REG_LIMITER,
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.mask1 = WM8776_LIM_TRANWIN_MASK,
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.flags = WM8776_FLAG_LIM,
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},
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[WM8776_CTL_LIM_MAXATTN] = {
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.name = "Limiter Maximum Attenuation Capture Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8776_maxatten_lim_tlv,
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.reg1 = WM8776_REG_LIMITER,
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.mask1 = WM8776_LIM_MAXATTEN_MASK,
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.min = 3,
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.max = 12,
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.flags = WM8776_FLAG_LIM | WM8776_FLAG_INVERT,
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},
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[WM8776_CTL_ALC_TGT] = {
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.name = "ALC Target Level Capture Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
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.tlv = wm8776_lct_tlv,
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.reg1 = WM8776_REG_ALCCTRL1,
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.mask1 = WM8776_ALC1_LCT_MASK,
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.max = 15,
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.flags = WM8776_FLAG_ALC,
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},
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[WM8776_CTL_ALC_ATK] = {
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.name = "ALC Attack Time Capture Enum",
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.type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
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.enum_names = { "8.40 ms", "16.8 ms", "33.6 ms", "67.2 ms",
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"134 ms", "269 ms", "538 ms", "1.08 s", "2.15 s",
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"4.3 s", "8.6 s" },
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.max = 11, /* .enum_names item count */
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.reg1 = WM8776_REG_ALCCTRL3,
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.mask1 = WM8776_ALC3_ATK_MASK,
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.flags = WM8776_FLAG_ALC,
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},
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[WM8776_CTL_ALC_DCY] = {
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.name = "ALC Decay Time Capture Enum",
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.type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
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.enum_names = { "33.5 ms", "67.0 ms", "134 ms", "268 ms",
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"536 ms", "1.07 s", "2.14 s", "4.29 s", "8.58 s",
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"17.2 s", "34.3 s" },
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.max = 11, /* .enum_names item count */
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.reg1 = WM8776_REG_ALCCTRL3,
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.mask1 = WM8776_ALC3_DCY_MASK,
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.flags = WM8776_FLAG_ALC,
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},
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[WM8776_CTL_ALC_MAXGAIN] = {
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.name = "ALC Maximum Gain Capture Volume",
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.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
|
||||
.tlv = wm8776_maxgain_tlv,
|
||||
.reg1 = WM8776_REG_ALCCTRL1,
|
||||
.mask1 = WM8776_ALC1_MAXGAIN_MASK,
|
||||
.min = 1,
|
||||
.max = 7,
|
||||
.flags = WM8776_FLAG_ALC,
|
||||
},
|
||||
[WM8776_CTL_ALC_MAXATTN] = {
|
||||
.name = "ALC Maximum Attenuation Capture Volume",
|
||||
.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
|
||||
.tlv = wm8776_maxatten_alc_tlv,
|
||||
.reg1 = WM8776_REG_LIMITER,
|
||||
.mask1 = WM8776_LIM_MAXATTEN_MASK,
|
||||
.min = 10,
|
||||
.max = 15,
|
||||
.flags = WM8776_FLAG_ALC | WM8776_FLAG_INVERT,
|
||||
},
|
||||
[WM8776_CTL_ALC_HLD] = {
|
||||
.name = "ALC Hold Time Capture Enum",
|
||||
.type = SNDRV_CTL_ELEM_TYPE_ENUMERATED,
|
||||
.enum_names = { "0 ms", "2.67 ms", "5.33 ms", "10.6 ms",
|
||||
"21.3 ms", "42.7 ms", "85.3 ms", "171 ms", "341 ms",
|
||||
"683 ms", "1.37 s", "2.73 s", "5.46 s", "10.9 s",
|
||||
"21.8 s", "43.7 s" },
|
||||
.max = 16, /* .enum_names item count */
|
||||
.reg1 = WM8776_REG_ALCCTRL2,
|
||||
.mask1 = WM8776_ALC2_HOLD_MASK,
|
||||
.flags = WM8776_FLAG_ALC,
|
||||
},
|
||||
[WM8776_CTL_NGT_SW] = {
|
||||
.name = "Noise Gate Capture Switch",
|
||||
.type = SNDRV_CTL_ELEM_TYPE_BOOLEAN,
|
||||
.reg1 = WM8776_REG_NOISEGATE,
|
||||
.mask1 = WM8776_NGAT_ENABLE,
|
||||
.flags = WM8776_FLAG_ALC,
|
||||
},
|
||||
[WM8776_CTL_NGT_THR] = {
|
||||
.name = "Noise Gate Threshold Capture Volume",
|
||||
.type = SNDRV_CTL_ELEM_TYPE_INTEGER,
|
||||
.tlv = wm8776_ngth_tlv,
|
||||
.reg1 = WM8776_REG_NOISEGATE,
|
||||
.mask1 = WM8776_NGAT_THR_MASK,
|
||||
.max = 7,
|
||||
.flags = WM8776_FLAG_ALC,
|
||||
},
|
||||
};
|
||||
|
||||
/* exported functions */
|
||||
|
||||
void snd_wm8776_init(struct snd_wm8776 *wm)
|
||||
{
|
||||
int i;
|
||||
static const u16 default_values[] = {
|
||||
0x000, 0x100, 0x000,
|
||||
0x000, 0x100, 0x000,
|
||||
0x000, 0x090, 0x000, 0x000,
|
||||
0x022, 0x022, 0x022,
|
||||
0x008, 0x0cf, 0x0cf, 0x07b, 0x000,
|
||||
0x032, 0x000, 0x0a6, 0x001, 0x001
|
||||
};
|
||||
|
||||
memcpy(wm->ctl, snd_wm8776_default_ctl, sizeof(wm->ctl));
|
||||
|
||||
snd_wm8776_write(wm, WM8776_REG_RESET, 0x00); /* reset */
|
||||
udelay(10);
|
||||
/* load defaults */
|
||||
for (i = 0; i < ARRAY_SIZE(default_values); i++)
|
||||
snd_wm8776_write(wm, i, default_values[i]);
|
||||
}
|
||||
|
||||
void snd_wm8776_resume(struct snd_wm8776 *wm)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < WM8776_REG_COUNT; i++)
|
||||
snd_wm8776_write(wm, i, wm->regs[i]);
|
||||
}
|
||||
|
||||
void snd_wm8776_set_dac_if(struct snd_wm8776 *wm, u16 dac)
|
||||
{
|
||||
snd_wm8776_write(wm, WM8776_REG_DACIFCTRL, dac);
|
||||
}
|
||||
|
||||
void snd_wm8776_set_adc_if(struct snd_wm8776 *wm, u16 adc)
|
||||
{
|
||||
snd_wm8776_write(wm, WM8776_REG_ADCIFCTRL, adc);
|
||||
}
|
||||
|
||||
void snd_wm8776_set_master_mode(struct snd_wm8776 *wm, u16 mode)
|
||||
{
|
||||
snd_wm8776_write(wm, WM8776_REG_MSTRCTRL, mode);
|
||||
}
|
||||
|
||||
void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power)
|
||||
{
|
||||
snd_wm8776_write(wm, WM8776_REG_PWRDOWN, power);
|
||||
}
|
||||
|
||||
void snd_wm8776_volume_restore(struct snd_wm8776 *wm)
|
||||
{
|
||||
u16 val = wm->regs[WM8776_REG_DACRVOL];
|
||||
/* restore volume after MCLK stopped */
|
||||
snd_wm8776_write(wm, WM8776_REG_DACRVOL, val | WM8776_VOL_UPDATE);
|
||||
}
|
||||
|
||||
/* mixer callbacks */
|
||||
|
||||
static int snd_wm8776_volume_info(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_info *uinfo)
|
||||
{
|
||||
struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
|
||||
int n = kcontrol->private_value;
|
||||
|
||||
uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
|
||||
uinfo->count = (wm->ctl[n].flags & WM8776_FLAG_STEREO) ? 2 : 1;
|
||||
uinfo->value.integer.min = wm->ctl[n].min;
|
||||
uinfo->value.integer.max = wm->ctl[n].max;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int snd_wm8776_enum_info(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_info *uinfo)
|
||||
{
|
||||
struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
|
||||
int n = kcontrol->private_value;
|
||||
|
||||
return snd_ctl_enum_info(uinfo, 1, wm->ctl[n].max,
|
||||
wm->ctl[n].enum_names);
|
||||
}
|
||||
|
||||
static int snd_wm8776_ctl_get(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
|
||||
int n = kcontrol->private_value;
|
||||
u16 val1, val2;
|
||||
|
||||
if (wm->ctl[n].get)
|
||||
wm->ctl[n].get(wm, &val1, &val2);
|
||||
else {
|
||||
val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1;
|
||||
val1 >>= __ffs(wm->ctl[n].mask1);
|
||||
if (wm->ctl[n].flags & WM8776_FLAG_STEREO) {
|
||||
val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2;
|
||||
val2 >>= __ffs(wm->ctl[n].mask2);
|
||||
if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE)
|
||||
val2 &= ~WM8776_VOL_UPDATE;
|
||||
}
|
||||
}
|
||||
if (wm->ctl[n].flags & WM8776_FLAG_INVERT) {
|
||||
val1 = wm->ctl[n].max - (val1 - wm->ctl[n].min);
|
||||
val2 = wm->ctl[n].max - (val2 - wm->ctl[n].min);
|
||||
}
|
||||
ucontrol->value.integer.value[0] = val1;
|
||||
if (wm->ctl[n].flags & WM8776_FLAG_STEREO)
|
||||
ucontrol->value.integer.value[1] = val2;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int snd_wm8776_ctl_put(struct snd_kcontrol *kcontrol,
|
||||
struct snd_ctl_elem_value *ucontrol)
|
||||
{
|
||||
struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol);
|
||||
int n = kcontrol->private_value;
|
||||
u16 val, regval1, regval2;
|
||||
|
||||
/* this also works for enum because value is an union */
|
||||
regval1 = ucontrol->value.integer.value[0];
|
||||
regval2 = ucontrol->value.integer.value[1];
|
||||
if (wm->ctl[n].flags & WM8776_FLAG_INVERT) {
|
||||
regval1 = wm->ctl[n].max - (regval1 - wm->ctl[n].min);
|
||||
regval2 = wm->ctl[n].max - (regval2 - wm->ctl[n].min);
|
||||
}
|
||||
if (wm->ctl[n].set)
|
||||
wm->ctl[n].set(wm, regval1, regval2);
|
||||
else {
|
||||
val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1;
|
||||
val |= regval1 << __ffs(wm->ctl[n].mask1);
|
||||
/* both stereo controls in one register */
|
||||
if (wm->ctl[n].flags & WM8776_FLAG_STEREO &&
|
||||
wm->ctl[n].reg1 == wm->ctl[n].reg2) {
|
||||
val &= ~wm->ctl[n].mask2;
|
||||
val |= regval2 << __ffs(wm->ctl[n].mask2);
|
||||
}
|
||||
snd_wm8776_write(wm, wm->ctl[n].reg1, val);
|
||||
/* stereo controls in different registers */
|
||||
if (wm->ctl[n].flags & WM8776_FLAG_STEREO &&
|
||||
wm->ctl[n].reg1 != wm->ctl[n].reg2) {
|
||||
val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2;
|
||||
val |= regval2 << __ffs(wm->ctl[n].mask2);
|
||||
if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE)
|
||||
val |= WM8776_VOL_UPDATE;
|
||||
snd_wm8776_write(wm, wm->ctl[n].reg2, val);
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int snd_wm8776_add_control(struct snd_wm8776 *wm, int num)
|
||||
{
|
||||
struct snd_kcontrol_new cont;
|
||||
struct snd_kcontrol *ctl;
|
||||
|
||||
memset(&cont, 0, sizeof(cont));
|
||||
cont.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
|
||||
cont.private_value = num;
|
||||
cont.name = wm->ctl[num].name;
|
||||
cont.access = SNDRV_CTL_ELEM_ACCESS_READWRITE;
|
||||
if (wm->ctl[num].flags & WM8776_FLAG_LIM ||
|
||||
wm->ctl[num].flags & WM8776_FLAG_ALC)
|
||||
cont.access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
|
||||
cont.tlv.p = NULL;
|
||||
cont.get = snd_wm8776_ctl_get;
|
||||
cont.put = snd_wm8776_ctl_put;
|
||||
|
||||
switch (wm->ctl[num].type) {
|
||||
case SNDRV_CTL_ELEM_TYPE_INTEGER:
|
||||
cont.info = snd_wm8776_volume_info;
|
||||
cont.access |= SNDRV_CTL_ELEM_ACCESS_TLV_READ;
|
||||
cont.tlv.p = wm->ctl[num].tlv;
|
||||
break;
|
||||
case SNDRV_CTL_ELEM_TYPE_BOOLEAN:
|
||||
wm->ctl[num].max = 1;
|
||||
if (wm->ctl[num].flags & WM8776_FLAG_STEREO)
|
||||
cont.info = snd_ctl_boolean_stereo_info;
|
||||
else
|
||||
cont.info = snd_ctl_boolean_mono_info;
|
||||
break;
|
||||
case SNDRV_CTL_ELEM_TYPE_ENUMERATED:
|
||||
cont.info = snd_wm8776_enum_info;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
ctl = snd_ctl_new1(&cont, wm);
|
||||
if (!ctl)
|
||||
return -ENOMEM;
|
||||
|
||||
return snd_ctl_add(wm->card, ctl);
|
||||
}
|
||||
|
||||
int snd_wm8776_build_controls(struct snd_wm8776 *wm)
|
||||
{
|
||||
int err, i;
|
||||
|
||||
for (i = 0; i < WM8776_CTL_COUNT; i++)
|
||||
if (wm->ctl[i].name) {
|
||||
err = snd_wm8776_add_control(wm, i);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,226 @@
|
|||
#ifndef __SOUND_WM8776_H
|
||||
#define __SOUND_WM8776_H
|
||||
|
||||
/*
|
||||
* ALSA driver for ICEnsemble VT17xx
|
||||
*
|
||||
* Lowlevel functions for WM8776 codec
|
||||
*
|
||||
* Copyright (c) 2012 Ondrej Zary <linux@rainbow-software.org>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#define WM8776_REG_HPLVOL 0x00
|
||||
#define WM8776_REG_HPRVOL 0x01
|
||||
#define WM8776_REG_HPMASTER 0x02
|
||||
#define WM8776_HPVOL_MASK 0x17f /* incl. update bit */
|
||||
#define WM8776_VOL_HPZCEN (1 << 7) /* zero cross detect */
|
||||
#define WM8776_VOL_UPDATE (1 << 8) /* update volume */
|
||||
#define WM8776_REG_DACLVOL 0x03
|
||||
#define WM8776_REG_DACRVOL 0x04
|
||||
#define WM8776_REG_DACMASTER 0x05
|
||||
#define WM8776_DACVOL_MASK 0x1ff /* incl. update bit */
|
||||
#define WM8776_REG_PHASESWAP 0x06
|
||||
#define WM8776_PHASE_INVERTL (1 << 0)
|
||||
#define WM8776_PHASE_INVERTR (1 << 1)
|
||||
#define WM8776_REG_DACCTRL1 0x07
|
||||
#define WM8776_DAC_DZCEN (1 << 0)
|
||||
#define WM8776_DAC_ATC (1 << 1)
|
||||
#define WM8776_DAC_IZD (1 << 2)
|
||||
#define WM8776_DAC_TOD (1 << 3)
|
||||
#define WM8776_DAC_PL_MASK 0xf0
|
||||
#define WM8776_DAC_PL_LL (1 << 4) /* L chan: L signal */
|
||||
#define WM8776_DAC_PL_LR (2 << 4) /* L chan: R signal */
|
||||
#define WM8776_DAC_PL_LB (3 << 4) /* L chan: both */
|
||||
#define WM8776_DAC_PL_RL (1 << 6) /* R chan: L signal */
|
||||
#define WM8776_DAC_PL_RR (2 << 6) /* R chan: R signal */
|
||||
#define WM8776_DAC_PL_RB (3 << 6) /* R chan: both */
|
||||
#define WM8776_REG_DACMUTE 0x08
|
||||
#define WM8776_DACMUTE (1 << 0)
|
||||
#define WM8776_REG_DACCTRL2 0x09
|
||||
#define WM8776_DAC2_DEEMPH (1 << 0)
|
||||
#define WM8776_DAC2_ZFLAG_DISABLE (0 << 1)
|
||||
#define WM8776_DAC2_ZFLAG_OWN (1 << 1)
|
||||
#define WM8776_DAC2_ZFLAG_BOTH (2 << 1)
|
||||
#define WM8776_DAC2_ZFLAG_EITHER (3 << 1)
|
||||
#define WM8776_REG_DACIFCTRL 0x0a
|
||||
#define WM8776_FMT_RIGHTJ (0 << 0)
|
||||
#define WM8776_FMT_LEFTJ (1 << 0)
|
||||
#define WM8776_FMT_I2S (2 << 0)
|
||||
#define WM8776_FMT_DSP (3 << 0)
|
||||
#define WM8776_FMT_DSP_LATE (1 << 2) /* in DSP mode */
|
||||
#define WM8776_FMT_LRC_INVERTED (1 << 2) /* in other modes */
|
||||
#define WM8776_FMT_BCLK_INVERTED (1 << 3)
|
||||
#define WM8776_FMT_16BIT (0 << 4)
|
||||
#define WM8776_FMT_20BIT (1 << 4)
|
||||
#define WM8776_FMT_24BIT (2 << 4)
|
||||
#define WM8776_FMT_32BIT (3 << 4)
|
||||
#define WM8776_REG_ADCIFCTRL 0x0b
|
||||
#define WM8776_FMT_ADCMCLK_INVERTED (1 << 6)
|
||||
#define WM8776_FMT_ADCHPD (1 << 8)
|
||||
#define WM8776_REG_MSTRCTRL 0x0c
|
||||
#define WM8776_IF_ADC256FS (2 << 0)
|
||||
#define WM8776_IF_ADC384FS (3 << 0)
|
||||
#define WM8776_IF_ADC512FS (4 << 0)
|
||||
#define WM8776_IF_ADC768FS (5 << 0)
|
||||
#define WM8776_IF_OVERSAMP64 (1 << 3)
|
||||
#define WM8776_IF_DAC128FS (0 << 4)
|
||||
#define WM8776_IF_DAC192FS (1 << 4)
|
||||
#define WM8776_IF_DAC256FS (2 << 4)
|
||||
#define WM8776_IF_DAC384FS (3 << 4)
|
||||
#define WM8776_IF_DAC512FS (4 << 4)
|
||||
#define WM8776_IF_DAC768FS (5 << 4)
|
||||
#define WM8776_IF_DAC_MASTER (1 << 7)
|
||||
#define WM8776_IF_ADC_MASTER (1 << 8)
|
||||
#define WM8776_REG_PWRDOWN 0x0d
|
||||
#define WM8776_PWR_PDWN (1 << 0)
|
||||
#define WM8776_PWR_ADCPD (1 << 1)
|
||||
#define WM8776_PWR_DACPD (1 << 2)
|
||||
#define WM8776_PWR_HPPD (1 << 3)
|
||||
#define WM8776_PWR_AINPD (1 << 6)
|
||||
#define WM8776_REG_ADCLVOL 0x0e
|
||||
#define WM8776_REG_ADCRVOL 0x0f
|
||||
#define WM8776_ADC_GAIN_MASK 0xff
|
||||
#define WM8776_ADC_ZCEN (1 << 8)
|
||||
#define WM8776_REG_ALCCTRL1 0x10
|
||||
#define WM8776_ALC1_LCT_MASK 0x0f /* 0=-16dB, 1=-15dB..15=-1dB */
|
||||
#define WM8776_ALC1_MAXGAIN_MASK 0x70 /* 0,1=0dB, 2=+4dB...7=+24dB */
|
||||
#define WM8776_ALC1_LCSEL_MASK 0x180
|
||||
#define WM8776_ALC1_LCSEL_LIMITER (0 << 7)
|
||||
#define WM8776_ALC1_LCSEL_ALCR (1 << 7)
|
||||
#define WM8776_ALC1_LCSEL_ALCL (2 << 7)
|
||||
#define WM8776_ALC1_LCSEL_ALCSTEREO (3 << 7)
|
||||
#define WM8776_REG_ALCCTRL2 0x11
|
||||
#define WM8776_ALC2_HOLD_MASK 0x0f /*0=0ms, 1=2.67ms, 2=5.33ms.. */
|
||||
#define WM8776_ALC2_ZCEN (1 << 7)
|
||||
#define WM8776_ALC2_LCEN (1 << 8)
|
||||
#define WM8776_REG_ALCCTRL3 0x12
|
||||
#define WM8776_ALC3_ATK_MASK 0x0f
|
||||
#define WM8776_ALC3_DCY_MASK 0xf0
|
||||
#define WM8776_ALC3_FDECAY (1 << 8)
|
||||
#define WM8776_REG_NOISEGATE 0x13
|
||||
#define WM8776_NGAT_ENABLE (1 << 0)
|
||||
#define WM8776_NGAT_THR_MASK 0x1c /*0=-78dB, 1=-72dB...7=-36dB */
|
||||
#define WM8776_REG_LIMITER 0x14
|
||||
#define WM8776_LIM_MAXATTEN_MASK 0x0f
|
||||
#define WM8776_LIM_TRANWIN_MASK 0x70 /*0=0us, 1=62.5us, 2=125us.. */
|
||||
#define WM8776_REG_ADCMUX 0x15
|
||||
#define WM8776_ADC_MUX_AIN1 (1 << 0)
|
||||
#define WM8776_ADC_MUX_AIN2 (1 << 1)
|
||||
#define WM8776_ADC_MUX_AIN3 (1 << 2)
|
||||
#define WM8776_ADC_MUX_AIN4 (1 << 3)
|
||||
#define WM8776_ADC_MUX_AIN5 (1 << 4)
|
||||
#define WM8776_ADC_MUTER (1 << 6)
|
||||
#define WM8776_ADC_MUTEL (1 << 7)
|
||||
#define WM8776_ADC_LRBOTH (1 << 8)
|
||||
#define WM8776_REG_OUTMUX 0x16
|
||||
#define WM8776_OUTMUX_DAC (1 << 0)
|
||||
#define WM8776_OUTMUX_AUX (1 << 1)
|
||||
#define WM8776_OUTMUX_BYPASS (1 << 2)
|
||||
#define WM8776_REG_RESET 0x17
|
||||
|
||||
#define WM8776_REG_COUNT 0x17 /* don't cache the RESET register */
|
||||
|
||||
struct snd_wm8776;
|
||||
|
||||
struct snd_wm8776_ops {
|
||||
void (*write)(struct snd_wm8776 *wm, u8 addr, u8 data);
|
||||
};
|
||||
|
||||
enum snd_wm8776_ctl_id {
|
||||
WM8776_CTL_DAC_VOL,
|
||||
WM8776_CTL_DAC_SW,
|
||||
WM8776_CTL_DAC_ZC_SW,
|
||||
WM8776_CTL_HP_VOL,
|
||||
WM8776_CTL_HP_SW,
|
||||
WM8776_CTL_HP_ZC_SW,
|
||||
WM8776_CTL_AUX_SW,
|
||||
WM8776_CTL_BYPASS_SW,
|
||||
WM8776_CTL_DAC_IZD_SW,
|
||||
WM8776_CTL_PHASE_SW,
|
||||
WM8776_CTL_DEEMPH_SW,
|
||||
WM8776_CTL_ADC_VOL,
|
||||
WM8776_CTL_ADC_SW,
|
||||
WM8776_CTL_INPUT1_SW,
|
||||
WM8776_CTL_INPUT2_SW,
|
||||
WM8776_CTL_INPUT3_SW,
|
||||
WM8776_CTL_INPUT4_SW,
|
||||
WM8776_CTL_INPUT5_SW,
|
||||
WM8776_CTL_AGC_SEL,
|
||||
WM8776_CTL_LIM_THR,
|
||||
WM8776_CTL_LIM_ATK,
|
||||
WM8776_CTL_LIM_DCY,
|
||||
WM8776_CTL_LIM_TRANWIN,
|
||||
WM8776_CTL_LIM_MAXATTN,
|
||||
WM8776_CTL_ALC_TGT,
|
||||
WM8776_CTL_ALC_ATK,
|
||||
WM8776_CTL_ALC_DCY,
|
||||
WM8776_CTL_ALC_MAXGAIN,
|
||||
WM8776_CTL_ALC_MAXATTN,
|
||||
WM8776_CTL_ALC_HLD,
|
||||
WM8776_CTL_NGT_SW,
|
||||
WM8776_CTL_NGT_THR,
|
||||
|
||||
WM8776_CTL_COUNT,
|
||||
};
|
||||
|
||||
#define WM8776_ENUM_MAX 16
|
||||
|
||||
#define WM8776_FLAG_STEREO (1 << 0)
|
||||
#define WM8776_FLAG_VOL_UPDATE (1 << 1)
|
||||
#define WM8776_FLAG_INVERT (1 << 2)
|
||||
#define WM8776_FLAG_LIM (1 << 3)
|
||||
#define WM8776_FLAG_ALC (1 << 4)
|
||||
|
||||
struct snd_wm8776_ctl {
|
||||
char *name;
|
||||
snd_ctl_elem_type_t type;
|
||||
const char *const enum_names[WM8776_ENUM_MAX];
|
||||
const unsigned int *tlv;
|
||||
u16 reg1, reg2, mask1, mask2, min, max, flags;
|
||||
void (*set)(struct snd_wm8776 *wm, u16 ch1, u16 ch2);
|
||||
void (*get)(struct snd_wm8776 *wm, u16 *ch1, u16 *ch2);
|
||||
};
|
||||
|
||||
enum snd_wm8776_agc_mode {
|
||||
WM8776_AGC_OFF,
|
||||
WM8776_AGC_LIM,
|
||||
WM8776_AGC_ALC_R,
|
||||
WM8776_AGC_ALC_L,
|
||||
WM8776_AGC_ALC_STEREO
|
||||
};
|
||||
|
||||
struct snd_wm8776 {
|
||||
struct snd_card *card;
|
||||
struct snd_wm8776_ctl ctl[WM8776_CTL_COUNT];
|
||||
enum snd_wm8776_agc_mode agc_mode;
|
||||
struct snd_wm8776_ops ops;
|
||||
u16 regs[WM8776_REG_COUNT]; /* 9-bit registers */
|
||||
};
|
||||
|
||||
|
||||
|
||||
void snd_wm8776_init(struct snd_wm8776 *wm);
|
||||
void snd_wm8776_resume(struct snd_wm8776 *wm);
|
||||
void snd_wm8776_set_dac_if(struct snd_wm8776 *wm, u16 dac);
|
||||
void snd_wm8776_set_adc_if(struct snd_wm8776 *wm, u16 adc);
|
||||
void snd_wm8776_set_master_mode(struct snd_wm8776 *wm, u16 mode);
|
||||
void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power);
|
||||
void snd_wm8776_volume_restore(struct snd_wm8776 *wm);
|
||||
int snd_wm8776_build_controls(struct snd_wm8776 *wm);
|
||||
|
||||
#endif /* __SOUND_WM8776_H */
|
||||
Loading…
Reference in New Issue