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Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-next 

Misc fixes and cleanups for 4.10. Highlights:
- Cursor fixes for radeon and amdgpu
- DPM fixes for some new SI variants
- Powerplay fixes
- Clock and powergating fixes

* 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (39 commits)
  drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well
  drm/amdgpu: use pin rather than pin_restricted in a few cases
  drm/amd/powerplay: use pr_debug to print function not implemented message
  drm/amd/amdgpu: Add gpr reading for GFX v7
  drm/amd/amdgpu: Add gpr reading for GFX v6
  drm/amd/amdgpu: Add debugfs support for reading GPRs (v2)
  drm/amd/amdgpu: export vbios information (v2)
  drm/amd/amdgpu: stored bios_size
  drm/amdgpu: update golden setting of tonga
  drm/amdgpu/si: load the proper firmware on 0x87 oland boards
  drm/amdgpu: add additional pci revision to dpm workaround
  drm/radeon/si: load the proper firmware on 0x87 oland boards
  drm/radeon: add additional pci revision to dpm workaround
  drm/amd/powerplay: Fix potential NULL pointer issue
  drm/amdgpu: Don't touch GFX hw during HW fini
  drm/amd/powerplay: Adjust the position of data size initial
  drm/amd/powerplay: Ignore smu buffer usage
  drm/amd/powerplay: cut digest part
  drm/amdgpu: drop redundant vi_mqd define
  drm/amdgpu: fix gtt available page num accounting
  ...
This commit is contained in:
Dave Airlie 2016-12-09 12:28:16 +10:00
parent 6f21890989 32859f7335
commit bfd5be0f9e
41 changed files with 557 additions and 436 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View File

@ -842,6 +842,8 @@ struct amdgpu_gfx_funcs {
uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
};
struct amdgpu_gfx {
@ -1330,6 +1332,7 @@ struct amdgpu_device {
/* BIOS */
uint8_t *bios;
uint32_t bios_size;
bool is_atom_bios;
struct amdgpu_bo *stollen_vga_memory;
uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
@ -1679,8 +1682,6 @@ uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev);
int amdgpu_ttm_global_init(struct amdgpu_device *adev);
int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
void amdgpu_program_register_sequence(struct amdgpu_device *adev,

6
drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c
View File

@ -74,6 +74,7 @@ static bool igp_read_bios_from_vram(struct amdgpu_device *adev)
iounmap(bios);
return false;
}
adev->bios_size = size;
memcpy_fromio(adev->bios, bios, size);
iounmap(bios);
return true;
@ -103,6 +104,7 @@ bool amdgpu_read_bios(struct amdgpu_device *adev)
pci_unmap_rom(adev->pdev, bios);
return false;
}
adev->bios_size = size;
memcpy_fromio(adev->bios, bios, size);
pci_unmap_rom(adev->pdev, bios);
return true;
@ -135,6 +137,7 @@ static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev)
DRM_ERROR("no memory to allocate for BIOS\n");
return false;
}
adev->bios_size = len;
/* read complete BIOS */
return amdgpu_asic_read_bios_from_rom(adev, adev->bios, len);
@ -159,6 +162,7 @@ static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
if (adev->bios == NULL) {
return false;
}
adev->bios_size = size;
return true;
}
@ -273,6 +277,7 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev)
kfree(adev->bios);
return false;
}
adev->bios_size = size;
return true;
}
#else
@ -334,6 +339,7 @@ static bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev)
}
adev->bios = kmemdup(&vbios->VbiosContent, vhdr->ImageLength, GFP_KERNEL);
adev->bios_size = vhdr->ImageLength;
ret = !!adev->bios;
out_unmap:

6
drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
View File

@ -723,7 +723,7 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
enum cgs_ucode_id type)
{
CGS_FUNC_ADEV;
uint16_t fw_version;
uint16_t fw_version = 0;
switch (type) {
case CGS_UCODE_ID_SDMA0:
@ -753,9 +753,11 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
case CGS_UCODE_ID_RLC_G:
fw_version = adev->gfx.rlc_fw_version;
break;
case CGS_UCODE_ID_STORAGE:
break;
default:
DRM_ERROR("firmware type %d do not have version\n", type);
fw_version = 0;
break;
}
return fw_version;
}

2
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
View File

@ -451,7 +451,7 @@ static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
return r;
if (bo->shadow)
r = amdgpu_cs_bo_validate(p, bo);
r = amdgpu_cs_bo_validate(p, bo->shadow);
return r;
}

87
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View File

@ -1470,20 +1470,26 @@ static int amdgpu_fini(struct amdgpu_device *adev)
amdgpu_wb_fini(adev);
amdgpu_vram_scratch_fini(adev);
}
/* ungate blocks before hw fini so that we can shutdown the blocks safely */
r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
AMD_CG_STATE_UNGATE);
if (r) {
DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
return r;
if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_UVD &&
adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_VCE) {
/* ungate blocks before hw fini so that we can shutdown the blocks safely */
r = adev->ip_blocks[i].version->funcs->set_clockgating_state((void *)adev,
AMD_CG_STATE_UNGATE);
if (r) {
DRM_ERROR("set_clockgating_state(ungate) of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
return r;
}
}
r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev);
/* XXX handle errors */
if (r) {
DRM_DEBUG("hw_fini of IP block <%s> failed %d\n",
adev->ip_blocks[i].version->funcs->name, r);
}
adev->ip_blocks[i].status.hw = false;
}
@ -2979,6 +2985,66 @@ static ssize_t amdgpu_debugfs_wave_read(struct file *f, char __user *buf,
return result;
}
static ssize_t amdgpu_debugfs_gpr_read(struct file *f, char __user *buf,
size_t size, loff_t *pos)
{
struct amdgpu_device *adev = f->f_inode->i_private;
int r;
ssize_t result = 0;
uint32_t offset, se, sh, cu, wave, simd, thread, bank, *data;
if (size & 3 || *pos & 3)
return -EINVAL;
/* decode offset */
offset = (*pos & 0xFFF); /* in dwords */
se = ((*pos >> 12) & 0xFF);
sh = ((*pos >> 20) & 0xFF);
cu = ((*pos >> 28) & 0xFF);
wave = ((*pos >> 36) & 0xFF);
simd = ((*pos >> 44) & 0xFF);
thread = ((*pos >> 52) & 0xFF);
bank = ((*pos >> 60) & 1);
data = kmalloc_array(1024, sizeof(*data), GFP_KERNEL);
if (!data)
return -ENOMEM;
/* switch to the specific se/sh/cu */
mutex_lock(&adev->grbm_idx_mutex);
amdgpu_gfx_select_se_sh(adev, se, sh, cu);
if (bank == 0) {
if (adev->gfx.funcs->read_wave_vgprs)
adev->gfx.funcs->read_wave_vgprs(adev, simd, wave, thread, offset, size>>2, data);
} else {
if (adev->gfx.funcs->read_wave_sgprs)
adev->gfx.funcs->read_wave_sgprs(adev, simd, wave, offset, size>>2, data);
}
amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
mutex_unlock(&adev->grbm_idx_mutex);
while (size) {
uint32_t value;
value = data[offset++];
r = put_user(value, (uint32_t *)buf);
if (r) {
result = r;
goto err;
}
result += 4;
buf += 4;
size -= 4;
}
err:
kfree(data);
return result;
}
static const struct file_operations amdgpu_debugfs_regs_fops = {
.owner = THIS_MODULE,
.read = amdgpu_debugfs_regs_read,
@ -3021,6 +3087,11 @@ static const struct file_operations amdgpu_debugfs_wave_fops = {
.read = amdgpu_debugfs_wave_read,
.llseek = default_llseek
};
static const struct file_operations amdgpu_debugfs_gpr_fops = {
.owner = THIS_MODULE,
.read = amdgpu_debugfs_gpr_read,
.llseek = default_llseek
};
static const struct file_operations *debugfs_regs[] = {
&amdgpu_debugfs_regs_fops,
@ -3030,6 +3101,7 @@ static const struct file_operations *debugfs_regs[] = {
&amdgpu_debugfs_gca_config_fops,
&amdgpu_debugfs_sensors_fops,
&amdgpu_debugfs_wave_fops,
&amdgpu_debugfs_gpr_fops,
};
static const char *debugfs_regs_names[] = {
@ -3040,6 +3112,7 @@ static const char *debugfs_regs_names[] = {
"amdgpu_gca_config",
"amdgpu_sensors",
"amdgpu_wave",
"amdgpu_gpr",
};
static int amdgpu_debugfs_regs_init(struct amdgpu_device *adev)

2
drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
View File

@ -187,7 +187,7 @@ int amdgpu_crtc_page_flip_target(struct drm_crtc *crtc,
goto cleanup;
}
r = amdgpu_bo_pin_restricted(new_abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base);
r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM, &base);
if (unlikely(r != 0)) {
r = -EINVAL;
DRM_ERROR("failed to pin new abo buffer before flip\n");

2
drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
View File

@ -171,7 +171,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
}
ret = amdgpu_bo_pin_restricted(abo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, NULL);
ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL);
if (ret) {
amdgpu_bo_unreserve(abo);
goto out_unref;

14
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
View File

@ -164,8 +164,10 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
spin_unlock(&mgr->lock);
node = kzalloc(sizeof(*node), GFP_KERNEL);
if (!node)
return -ENOMEM;
if (!node) {
r = -ENOMEM;
goto err_out;
}
node->start = AMDGPU_BO_INVALID_OFFSET;
node->size = mem->num_pages;
@ -176,12 +178,20 @@ static int amdgpu_gtt_mgr_new(struct ttm_mem_type_manager *man,
if (unlikely(r)) {
kfree(node);
mem->mm_node = NULL;
r = 0;
goto err_out;
}
} else {
mem->start = node->start;
}
return 0;
err_out:
spin_lock(&mgr->lock);
mgr->available += mem->num_pages;
spin_unlock(&mgr->lock);
return r;
}
/**

26
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@ -544,6 +544,32 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
return copy_to_user(out, &vce_clk_table,
min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
}
case AMDGPU_INFO_VBIOS: {
uint32_t bios_size = adev->bios_size;
switch (info->vbios_info.type) {
case AMDGPU_INFO_VBIOS_SIZE:
return copy_to_user(out, &bios_size,
min((size_t)size, sizeof(bios_size)))
? -EFAULT : 0;
case AMDGPU_INFO_VBIOS_IMAGE: {
uint8_t *bios;
uint32_t bios_offset = info->vbios_info.offset;
if (bios_offset >= bios_size)
return -EINVAL;
bios = adev->bios + bios_offset;
return copy_to_user(out, bios,
min((size_t)size, (size_t)(bios_size - bios_offset)))
? -EFAULT : 0;
}
default:
DRM_DEBUG_KMS("Invalid request %d\n",
info->vbios_info.type);
return -EINVAL;
}
}
default:
DRM_DEBUG_KMS("Invalid request %d\n", info->query);
return -EINVAL;

12
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
View File

@ -34,7 +34,6 @@
#include <ttm/ttm_placement.h>
#include <ttm/ttm_module.h>
#include <ttm/ttm_page_alloc.h>
#include <ttm/ttm_memory.h>
#include <drm/drmP.h>
#include <drm/amdgpu_drm.h>
#include <linux/seq_file.h>
@ -65,7 +64,7 @@ static void amdgpu_ttm_mem_global_release(struct drm_global_reference *ref)
ttm_mem_global_release(ref->object);
}
int amdgpu_ttm_global_init(struct amdgpu_device *adev)
static int amdgpu_ttm_global_init(struct amdgpu_device *adev)
{
struct drm_global_reference *global_ref;
struct amdgpu_ring *ring;
@ -1151,6 +1150,10 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
unsigned i, j;
int r;
r = amdgpu_ttm_global_init(adev);
if (r) {
return r;
}
/* No others user of address space so set it to 0 */
r = ttm_bo_device_init(&adev->mman.bdev,
adev->mman.bo_global_ref.ref.object,
@ -1650,8 +1653,3 @@ static void amdgpu_ttm_debugfs_fini(struct amdgpu_device *adev)
#endif
}
u64 amdgpu_ttm_get_gtt_mem_size(struct amdgpu_device *adev)
{
return ttm_get_kernel_zone_memory_size(adev->mman.mem_global_ref.object);
}

2
drivers/gpu/drm/amd/amdgpu/ci_dpm.c
View File

@ -6083,7 +6083,7 @@ ci_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
activity_percent = activity_percent > 100 ? 100 : activity_percent;
}
seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
seq_printf(m, "uvd %sabled\n", pi->uvd_power_gated ? "dis" : "en");
seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
seq_printf(m, "power level avg sclk: %u mclk: %u\n",
sclk, mclk);

25
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
View File

@ -2493,6 +2493,9 @@ static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
struct amdgpu_device *adev = crtc->dev->dev_private;
int xorigin = 0, yorigin = 0;
amdgpu_crtc->cursor_x = x;
amdgpu_crtc->cursor_y = y;
/* avivo cursor are offset into the total surface */
x += crtc->x;
y += crtc->y;
@ -2509,11 +2512,6 @@ static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
amdgpu_crtc->cursor_x = x;
amdgpu_crtc->cursor_y = y;
return 0;
}
@ -2539,6 +2537,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
int32_t hot_y)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
struct drm_gem_object *obj;
struct amdgpu_bo *aobj;
int ret;
@ -2577,9 +2576,6 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
return ret;
}
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
dce_v10_0_lock_cursor(crtc, true);
if (hot_x != amdgpu_crtc->cursor_hot_x ||
@ -2595,6 +2591,14 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
amdgpu_crtc->cursor_hot_y = hot_y;
}
if (width != amdgpu_crtc->cursor_width ||
height != amdgpu_crtc->cursor_height) {
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
(width - 1) << 16 | (height - 1));
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
}
dce_v10_0_show_cursor(crtc);
dce_v10_0_lock_cursor(crtc, false);
@ -2616,6 +2620,7 @@ unpin:
static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
if (amdgpu_crtc->cursor_bo) {
dce_v10_0_lock_cursor(crtc, true);
@ -2623,6 +2628,10 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
amdgpu_crtc->cursor_y);
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
(amdgpu_crtc->cursor_width - 1) << 16 |
(amdgpu_crtc->cursor_height - 1));
dce_v10_0_show_cursor(crtc);
dce_v10_0_lock_cursor(crtc, false);

25
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
View File

@ -2509,6 +2509,9 @@ static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
struct amdgpu_device *adev = crtc->dev->dev_private;
int xorigin = 0, yorigin = 0;
amdgpu_crtc->cursor_x = x;
amdgpu_crtc->cursor_y = y;
/* avivo cursor are offset into the total surface */
x += crtc->x;
y += crtc->y;
@ -2525,11 +2528,6 @@ static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
amdgpu_crtc->cursor_x = x;
amdgpu_crtc->cursor_y = y;
return 0;
}
@ -2555,6 +2553,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
int32_t hot_y)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
struct drm_gem_object *obj;
struct amdgpu_bo *aobj;
int ret;
@ -2593,9 +2592,6 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
return ret;
}
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
dce_v11_0_lock_cursor(crtc, true);
if (hot_x != amdgpu_crtc->cursor_hot_x ||
@ -2611,6 +2607,14 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
amdgpu_crtc->cursor_hot_y = hot_y;
}
if (width != amdgpu_crtc->cursor_width ||
height != amdgpu_crtc->cursor_height) {
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
(width - 1) << 16 | (height - 1));
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
}
dce_v11_0_show_cursor(crtc);
dce_v11_0_lock_cursor(crtc, false);
@ -2632,6 +2636,7 @@ unpin:
static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
if (amdgpu_crtc->cursor_bo) {
dce_v11_0_lock_cursor(crtc, true);
@ -2639,6 +2644,10 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
amdgpu_crtc->cursor_y);
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
(amdgpu_crtc->cursor_width - 1) << 16 |
(amdgpu_crtc->cursor_height - 1));
dce_v11_0_show_cursor(crtc);
dce_v11_0_lock_cursor(crtc, false);

33
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
View File

@ -460,9 +460,8 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
for (i = 0; i < adev->mode_info.num_crtc; i++) {
if (save->crtc_enabled[i]) {
tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
if ((tmp & 0x7) != 3) {
if ((tmp & 0x7) != 0) {
tmp &= ~0x7;
tmp |= 0x3;
WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
}
tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
@ -1860,7 +1859,8 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
struct amdgpu_device *adev = crtc->dev->dev_private;
int xorigin = 0, yorigin = 0;
int w = amdgpu_crtc->cursor_width;
amdgpu_crtc->cursor_x = x;
amdgpu_crtc->cursor_y = y;
/* avivo cursor are offset into the total surface */
x += crtc->x;
@ -1878,11 +1878,7 @@ static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
amdgpu_crtc->cursor_x = x;
amdgpu_crtc->cursor_y = y;
return 0;
}
@ -1907,6 +1903,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
int32_t hot_y)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
struct drm_gem_object *obj;
struct amdgpu_bo *aobj;
int ret;
@ -1945,12 +1942,11 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
return ret;
}
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
dce_v6_0_lock_cursor(crtc, true);
if (hot_x != amdgpu_crtc->cursor_hot_x ||
if (width != amdgpu_crtc->cursor_width ||
height != amdgpu_crtc->cursor_height ||
hot_x != amdgpu_crtc->cursor_hot_x ||
hot_y != amdgpu_crtc->cursor_hot_y) {
int x, y;
@ -1959,10 +1955,20 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
dce_v6_0_cursor_move_locked(crtc, x, y);
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
amdgpu_crtc->cursor_hot_x = hot_x;
amdgpu_crtc->cursor_hot_y = hot_y;
}
if (width != amdgpu_crtc->cursor_width ||
height != amdgpu_crtc->cursor_height) {
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
(width - 1) << 16 | (height - 1));
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
}
dce_v6_0_show_cursor(crtc);
dce_v6_0_lock_cursor(crtc, false);
@ -1984,6 +1990,7 @@ unpin:
static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
if (amdgpu_crtc->cursor_bo) {
dce_v6_0_lock_cursor(crtc, true);
@ -1991,6 +1998,10 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
amdgpu_crtc->cursor_y);
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
(amdgpu_crtc->cursor_width - 1) << 16 |
(amdgpu_crtc->cursor_height - 1));
dce_v6_0_show_cursor(crtc);
dce_v6_0_lock_cursor(crtc, false);
}

27
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
View File

@ -2344,6 +2344,9 @@ static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
struct amdgpu_device *adev = crtc->dev->dev_private;
int xorigin = 0, yorigin = 0;
amdgpu_crtc->cursor_x = x;
amdgpu_crtc->cursor_y = y;
/* avivo cursor are offset into the total surface */
x += crtc->x;
y += crtc->y;
@ -2360,11 +2363,6 @@ static int dce_v8_0_cursor_move_locked(struct drm_crtc *crtc,
WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
amdgpu_crtc->cursor_x = x;
amdgpu_crtc->cursor_y = y;
return 0;
}
@ -2390,6 +2388,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
int32_t hot_y)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
struct drm_gem_object *obj;
struct amdgpu_bo *aobj;
int ret;
@ -2428,9 +2427,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
return ret;
}
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
dce_v8_0_lock_cursor(crtc, true);
if (hot_x != amdgpu_crtc->cursor_hot_x ||
@ -2442,10 +2438,20 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
dce_v8_0_cursor_move_locked(crtc, x, y);
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
amdgpu_crtc->cursor_hot_x = hot_x;
amdgpu_crtc->cursor_hot_y = hot_y;
}
if (width != amdgpu_crtc->cursor_width ||
height != amdgpu_crtc->cursor_height) {
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
(width - 1) << 16 | (height - 1));
amdgpu_crtc->cursor_width = width;
amdgpu_crtc->cursor_height = height;
}
dce_v8_0_show_cursor(crtc);
dce_v8_0_lock_cursor(crtc, false);
@ -2467,6 +2473,7 @@ unpin:
static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
{
struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
struct amdgpu_device *adev = crtc->dev->dev_private;
if (amdgpu_crtc->cursor_bo) {
dce_v8_0_lock_cursor(crtc, true);
@ -2474,6 +2481,10 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc)
dce_v8_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
amdgpu_crtc->cursor_y);
WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
(amdgpu_crtc->cursor_width - 1) << 16 |
(amdgpu_crtc->cursor_height - 1));
dce_v8_0_show_cursor(crtc);
dce_v8_0_lock_cursor(crtc, false);

25
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
View File

@ -2827,6 +2827,21 @@ static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_
return RREG32(mmSQ_IND_DATA);
}
static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
uint32_t wave, uint32_t thread,
uint32_t regno, uint32_t num, uint32_t *out)
{
WREG32(mmSQ_IND_INDEX,
(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
(regno << SQ_IND_INDEX__INDEX__SHIFT) |
(thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
(SQ_IND_INDEX__FORCE_READ_MASK) |
(SQ_IND_INDEX__AUTO_INCR_MASK));
while (num--)
*(out++) = RREG32(mmSQ_IND_DATA);
}
static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
{
/* type 0 wave data */
@ -2851,10 +2866,20 @@ static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
}
static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
uint32_t wave, uint32_t start,
uint32_t size, uint32_t *dst)
{
wave_read_regs(
adev, simd, wave, 0,
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
}
static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v6_0_select_se_sh,
.read_wave_data = &gfx_v6_0_read_wave_data,
.read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
};
static int gfx_v6_0_early_init(void *handle)

25
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
View File

@ -4380,6 +4380,21 @@ static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_
return RREG32(mmSQ_IND_DATA);
}
static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
uint32_t wave, uint32_t thread,
uint32_t regno, uint32_t num, uint32_t *out)
{
WREG32(mmSQ_IND_INDEX,
(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
(regno << SQ_IND_INDEX__INDEX__SHIFT) |
(thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
(SQ_IND_INDEX__FORCE_READ_MASK) |
(SQ_IND_INDEX__AUTO_INCR_MASK));
while (num--)
*(out++) = RREG32(mmSQ_IND_DATA);
}
static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
{
/* type 0 wave data */
@ -4404,10 +4419,20 @@ static void gfx_v7_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
}
static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
uint32_t wave, uint32_t start,
uint32_t size, uint32_t *dst)
{
wave_read_regs(
adev, simd, wave, 0,
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
}
static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v7_0_select_se_sh,
.read_wave_data = &gfx_v7_0_read_wave_data,
.read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
};
static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {

363
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View File

@ -25,6 +25,7 @@
#include "amdgpu.h"
#include "amdgpu_gfx.h"
#include "vi.h"
#include "vi_structs.h"
#include "vid.h"
#include "amdgpu_ucode.h"
#include "amdgpu_atombios.h"
@ -167,6 +168,7 @@ static const u32 golden_settings_tonga_a11[] =
mmPA_SC_ENHANCE, 0xffffffff, 0x20000001,
mmPA_SC_FIFO_DEPTH_CNTL, 0x000003ff, 0x000000fc,
mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000,
mmRLC_CGCG_CGLS_CTRL, 0x00000003, 0x0000003c,
mmSQ_RANDOM_WAVE_PRI, 0x001fffff, 0x000006fd,
mmTA_CNTL_AUX, 0x000f000f, 0x000b0000,
mmTCC_CTRL, 0x00100000, 0xf31fff7f,
@ -1371,7 +1373,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
if (adev->gfx.mec.hpd_eop_obj == NULL) {
r = amdgpu_bo_create(adev,
adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2,
adev->gfx.mec.num_queue * MEC_HPD_SIZE,
PAGE_SIZE, true,
AMDGPU_GEM_DOMAIN_GTT, 0, NULL, NULL,
&adev->gfx.mec.hpd_eop_obj);
@ -1400,7 +1402,7 @@ static int gfx_v8_0_mec_init(struct amdgpu_device *adev)
return r;
}
memset(hpd, 0, adev->gfx.mec.num_mec *adev->gfx.mec.num_pipe * MEC_HPD_SIZE * 2);
memset(hpd, 0, adev->gfx.mec.num_queue * MEC_HPD_SIZE);
amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
@ -4469,267 +4471,6 @@ static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
return 0;
}
struct vi_mqd {
uint32_t header; /* ordinal0 */
uint32_t compute_dispatch_initiator; /* ordinal1 */
uint32_t compute_dim_x; /* ordinal2 */
uint32_t compute_dim_y; /* ordinal3 */
uint32_t compute_dim_z; /* ordinal4 */
uint32_t compute_start_x; /* ordinal5 */
uint32_t compute_start_y; /* ordinal6 */
uint32_t compute_start_z; /* ordinal7 */
uint32_t compute_num_thread_x; /* ordinal8 */
uint32_t compute_num_thread_y; /* ordinal9 */
uint32_t compute_num_thread_z; /* ordinal10 */
uint32_t compute_pipelinestat_enable; /* ordinal11 */
uint32_t compute_perfcount_enable; /* ordinal12 */
uint32_t compute_pgm_lo; /* ordinal13 */
uint32_t compute_pgm_hi; /* ordinal14 */
uint32_t compute_tba_lo; /* ordinal15 */
uint32_t compute_tba_hi; /* ordinal16 */
uint32_t compute_tma_lo; /* ordinal17 */
uint32_t compute_tma_hi; /* ordinal18 */
uint32_t compute_pgm_rsrc1; /* ordinal19 */
uint32_t compute_pgm_rsrc2; /* ordinal20 */
uint32_t compute_vmid; /* ordinal21 */
uint32_t compute_resource_limits; /* ordinal22 */
uint32_t compute_static_thread_mgmt_se0; /* ordinal23 */
uint32_t compute_static_thread_mgmt_se1; /* ordinal24 */
uint32_t compute_tmpring_size; /* ordinal25 */
uint32_t compute_static_thread_mgmt_se2; /* ordinal26 */
uint32_t compute_static_thread_mgmt_se3; /* ordinal27 */
uint32_t compute_restart_x; /* ordinal28 */
uint32_t compute_restart_y; /* ordinal29 */
uint32_t compute_restart_z; /* ordinal30 */
uint32_t compute_thread_trace_enable; /* ordinal31 */
uint32_t compute_misc_reserved; /* ordinal32 */
uint32_t compute_dispatch_id; /* ordinal33 */
uint32_t compute_threadgroup_id; /* ordinal34 */
uint32_t compute_relaunch; /* ordinal35 */
uint32_t compute_wave_restore_addr_lo; /* ordinal36 */
uint32_t compute_wave_restore_addr_hi; /* ordinal37 */
uint32_t compute_wave_restore_control; /* ordinal38 */
uint32_t reserved9; /* ordinal39 */
uint32_t reserved10; /* ordinal40 */
uint32_t reserved11; /* ordinal41 */
uint32_t reserved12; /* ordinal42 */
uint32_t reserved13; /* ordinal43 */
uint32_t reserved14; /* ordinal44 */
uint32_t reserved15; /* ordinal45 */
uint32_t reserved16; /* ordinal46 */
uint32_t reserved17; /* ordinal47 */
uint32_t reserved18; /* ordinal48 */
uint32_t reserved19; /* ordinal49 */
uint32_t reserved20; /* ordinal50 */
uint32_t reserved21; /* ordinal51 */
uint32_t reserved22; /* ordinal52 */
uint32_t reserved23; /* ordinal53 */
uint32_t reserved24; /* ordinal54 */
uint32_t reserved25; /* ordinal55 */
uint32_t reserved26; /* ordinal56 */
uint32_t reserved27; /* ordinal57 */
uint32_t reserved28; /* ordinal58 */
uint32_t reserved29; /* ordinal59 */
uint32_t reserved30; /* ordinal60 */
uint32_t reserved31; /* ordinal61 */
uint32_t reserved32; /* ordinal62 */
uint32_t reserved33; /* ordinal63 */
uint32_t reserved34; /* ordinal64 */
uint32_t compute_user_data_0; /* ordinal65 */
uint32_t compute_user_data_1; /* ordinal66 */
uint32_t compute_user_data_2; /* ordinal67 */
uint32_t compute_user_data_3; /* ordinal68 */
uint32_t compute_user_data_4; /* ordinal69 */
uint32_t compute_user_data_5; /* ordinal70 */
uint32_t compute_user_data_6; /* ordinal71 */
uint32_t compute_user_data_7; /* ordinal72 */
uint32_t compute_user_data_8; /* ordinal73 */
uint32_t compute_user_data_9; /* ordinal74 */
uint32_t compute_user_data_10; /* ordinal75 */
uint32_t compute_user_data_11; /* ordinal76 */
uint32_t compute_user_data_12; /* ordinal77 */
uint32_t compute_user_data_13; /* ordinal78 */
uint32_t compute_user_data_14; /* ordinal79 */
uint32_t compute_user_data_15; /* ordinal80 */
uint32_t cp_compute_csinvoc_count_lo; /* ordinal81 */
uint32_t cp_compute_csinvoc_count_hi; /* ordinal82 */
uint32_t reserved35; /* ordinal83 */
uint32_t reserved36; /* ordinal84 */
uint32_t reserved37; /* ordinal85 */
uint32_t cp_mqd_query_time_lo; /* ordinal86 */
uint32_t cp_mqd_query_time_hi; /* ordinal87 */
uint32_t cp_mqd_connect_start_time_lo; /* ordinal88 */
uint32_t cp_mqd_connect_start_time_hi; /* ordinal89 */
uint32_t cp_mqd_connect_end_time_lo; /* ordinal90 */
uint32_t cp_mqd_connect_end_time_hi; /* ordinal91 */
uint32_t cp_mqd_connect_end_wf_count; /* ordinal92 */
uint32_t cp_mqd_connect_end_pq_rptr; /* ordinal93 */
uint32_t cp_mqd_connect_end_pq_wptr; /* ordinal94 */
uint32_t cp_mqd_connect_end_ib_rptr; /* ordinal95 */
uint32_t reserved38; /* ordinal96 */
uint32_t reserved39; /* ordinal97 */
uint32_t cp_mqd_save_start_time_lo; /* ordinal98 */
uint32_t cp_mqd_save_start_time_hi; /* ordinal99 */
uint32_t cp_mqd_save_end_time_lo; /* ordinal100 */
uint32_t cp_mqd_save_end_time_hi; /* ordinal101 */
uint32_t cp_mqd_restore_start_time_lo; /* ordinal102 */
uint32_t cp_mqd_restore_start_time_hi; /* ordinal103 */
uint32_t cp_mqd_restore_end_time_lo; /* ordinal104 */
uint32_t cp_mqd_restore_end_time_hi; /* ordinal105 */
uint32_t reserved40; /* ordinal106 */
uint32_t reserved41; /* ordinal107 */
uint32_t gds_cs_ctxsw_cnt0; /* ordinal108 */
uint32_t gds_cs_ctxsw_cnt1; /* ordinal109 */
uint32_t gds_cs_ctxsw_cnt2; /* ordinal110 */
uint32_t gds_cs_ctxsw_cnt3; /* ordinal111 */
uint32_t reserved42; /* ordinal112 */
uint32_t reserved43; /* ordinal113 */
uint32_t cp_pq_exe_status_lo; /* ordinal114 */
uint32_t cp_pq_exe_status_hi; /* ordinal115 */
uint32_t cp_packet_id_lo; /* ordinal116 */
uint32_t cp_packet_id_hi; /* ordinal117 */
uint32_t cp_packet_exe_status_lo; /* ordinal118 */
uint32_t cp_packet_exe_status_hi; /* ordinal119 */
uint32_t gds_save_base_addr_lo; /* ordinal120 */
uint32_t gds_save_base_addr_hi; /* ordinal121 */
uint32_t gds_save_mask_lo; /* ordinal122 */
uint32_t gds_save_mask_hi; /* ordinal123 */
uint32_t ctx_save_base_addr_lo; /* ordinal124 */
uint32_t ctx_save_base_addr_hi; /* ordinal125 */
uint32_t reserved44; /* ordinal126 */
uint32_t reserved45; /* ordinal127 */
uint32_t cp_mqd_base_addr_lo; /* ordinal128 */
uint32_t cp_mqd_base_addr_hi; /* ordinal129 */
uint32_t cp_hqd_active; /* ordinal130 */
uint32_t cp_hqd_vmid; /* ordinal131 */
uint32_t cp_hqd_persistent_state; /* ordinal132 */
uint32_t cp_hqd_pipe_priority; /* ordinal133 */
uint32_t cp_hqd_queue_priority; /* ordinal134 */
uint32_t cp_hqd_quantum; /* ordinal135 */
uint32_t cp_hqd_pq_base_lo; /* ordinal136 */
uint32_t cp_hqd_pq_base_hi; /* ordinal137 */
uint32_t cp_hqd_pq_rptr; /* ordinal138 */
uint32_t cp_hqd_pq_rptr_report_addr_lo; /* ordinal139 */
uint32_t cp_hqd_pq_rptr_report_addr_hi; /* ordinal140 */
uint32_t cp_hqd_pq_wptr_poll_addr; /* ordinal141 */
uint32_t cp_hqd_pq_wptr_poll_addr_hi; /* ordinal142 */
uint32_t cp_hqd_pq_doorbell_control; /* ordinal143 */
uint32_t cp_hqd_pq_wptr; /* ordinal144 */
uint32_t cp_hqd_pq_control; /* ordinal145 */
uint32_t cp_hqd_ib_base_addr_lo; /* ordinal146 */
uint32_t cp_hqd_ib_base_addr_hi; /* ordinal147 */
uint32_t cp_hqd_ib_rptr; /* ordinal148 */
uint32_t cp_hqd_ib_control; /* ordinal149 */
uint32_t cp_hqd_iq_timer; /* ordinal150 */
uint32_t cp_hqd_iq_rptr; /* ordinal151 */
uint32_t cp_hqd_dequeue_request; /* ordinal152 */
uint32_t cp_hqd_dma_offload; /* ordinal153 */
uint32_t cp_hqd_sema_cmd; /* ordinal154 */
uint32_t cp_hqd_msg_type; /* ordinal155 */
uint32_t cp_hqd_atomic0_preop_lo; /* ordinal156 */
uint32_t cp_hqd_atomic0_preop_hi; /* ordinal157 */
uint32_t cp_hqd_atomic1_preop_lo; /* ordinal158 */
uint32_t cp_hqd_atomic1_preop_hi; /* ordinal159 */
uint32_t cp_hqd_hq_status0; /* ordinal160 */
uint32_t cp_hqd_hq_control0; /* ordinal161 */
uint32_t cp_mqd_control; /* ordinal162 */
uint32_t cp_hqd_hq_status1; /* ordinal163 */
uint32_t cp_hqd_hq_control1; /* ordinal164 */
uint32_t cp_hqd_eop_base_addr_lo; /* ordinal165 */
uint32_t cp_hqd_eop_base_addr_hi; /* ordinal166 */
uint32_t cp_hqd_eop_control; /* ordinal167 */
uint32_t cp_hqd_eop_rptr; /* ordinal168 */
uint32_t cp_hqd_eop_wptr; /* ordinal169 */
uint32_t cp_hqd_eop_done_events; /* ordinal170 */
uint32_t cp_hqd_ctx_save_base_addr_lo; /* ordinal171 */
uint32_t cp_hqd_ctx_save_base_addr_hi; /* ordinal172 */
uint32_t cp_hqd_ctx_save_control; /* ordinal173 */
uint32_t cp_hqd_cntl_stack_offset; /* ordinal174 */
uint32_t cp_hqd_cntl_stack_size; /* ordinal175 */
uint32_t cp_hqd_wg_state_offset; /* ordinal176 */
uint32_t cp_hqd_ctx_save_size; /* ordinal177 */
uint32_t cp_hqd_gds_resource_state; /* ordinal178 */
uint32_t cp_hqd_error; /* ordinal179 */
uint32_t cp_hqd_eop_wptr_mem; /* ordinal180 */
uint32_t cp_hqd_eop_dones; /* ordinal181 */
uint32_t reserved46; /* ordinal182 */
uint32_t reserved47; /* ordinal183 */
uint32_t reserved48; /* ordinal184 */
uint32_t reserved49; /* ordinal185 */
uint32_t reserved50; /* ordinal186 */
uint32_t reserved51; /* ordinal187 */
uint32_t reserved52; /* ordinal188 */
uint32_t reserved53; /* ordinal189 */
uint32_t reserved54; /* ordinal190 */
uint32_t reserved55; /* ordinal191 */
uint32_t iqtimer_pkt_header; /* ordinal192 */
uint32_t iqtimer_pkt_dw0; /* ordinal193 */
uint32_t iqtimer_pkt_dw1; /* ordinal194 */
uint32_t iqtimer_pkt_dw2; /* ordinal195 */
uint32_t iqtimer_pkt_dw3; /* ordinal196 */
uint32_t iqtimer_pkt_dw4; /* ordinal197 */
uint32_t iqtimer_pkt_dw5; /* ordinal198 */
uint32_t iqtimer_pkt_dw6; /* ordinal199 */
uint32_t iqtimer_pkt_dw7; /* ordinal200 */
uint32_t iqtimer_pkt_dw8; /* ordinal201 */
uint32_t iqtimer_pkt_dw9; /* ordinal202 */
uint32_t iqtimer_pkt_dw10; /* ordinal203 */
uint32_t iqtimer_pkt_dw11; /* ordinal204 */
uint32_t iqtimer_pkt_dw12; /* ordinal205 */
uint32_t iqtimer_pkt_dw13; /* ordinal206 */
uint32_t iqtimer_pkt_dw14; /* ordinal207 */
uint32_t iqtimer_pkt_dw15; /* ordinal208 */
uint32_t iqtimer_pkt_dw16; /* ordinal209 */
uint32_t iqtimer_pkt_dw17; /* ordinal210 */
uint32_t iqtimer_pkt_dw18; /* ordinal211 */
uint32_t iqtimer_pkt_dw19; /* ordinal212 */
uint32_t iqtimer_pkt_dw20; /* ordinal213 */
uint32_t iqtimer_pkt_dw21; /* ordinal214 */
uint32_t iqtimer_pkt_dw22; /* ordinal215 */
uint32_t iqtimer_pkt_dw23; /* ordinal216 */
uint32_t iqtimer_pkt_dw24; /* ordinal217 */
uint32_t iqtimer_pkt_dw25; /* ordinal218 */
uint32_t iqtimer_pkt_dw26; /* ordinal219 */
uint32_t iqtimer_pkt_dw27; /* ordinal220 */
uint32_t iqtimer_pkt_dw28; /* ordinal221 */
uint32_t iqtimer_pkt_dw29; /* ordinal222 */
uint32_t iqtimer_pkt_dw30; /* ordinal223 */
uint32_t iqtimer_pkt_dw31; /* ordinal224 */
uint32_t reserved56; /* ordinal225 */
uint32_t reserved57; /* ordinal226 */
uint32_t reserved58; /* ordinal227 */
uint32_t set_resources_header; /* ordinal228 */
uint32_t set_resources_dw1; /* ordinal229 */
uint32_t set_resources_dw2; /* ordinal230 */
uint32_t set_resources_dw3; /* ordinal231 */
uint32_t set_resources_dw4; /* ordinal232 */
uint32_t set_resources_dw5; /* ordinal233 */
uint32_t set_resources_dw6; /* ordinal234 */
uint32_t set_resources_dw7; /* ordinal235 */
uint32_t reserved59; /* ordinal236 */
uint32_t reserved60; /* ordinal237 */
uint32_t reserved61; /* ordinal238 */
uint32_t reserved62; /* ordinal239 */
uint32_t reserved63; /* ordinal240 */
uint32_t reserved64; /* ordinal241 */
uint32_t reserved65; /* ordinal242 */
uint32_t reserved66; /* ordinal243 */
uint32_t reserved67; /* ordinal244 */
uint32_t reserved68; /* ordinal245 */
uint32_t reserved69; /* ordinal246 */
uint32_t reserved70; /* ordinal247 */
uint32_t reserved71; /* ordinal248 */
uint32_t reserved72; /* ordinal249 */
uint32_t reserved73; /* ordinal250 */
uint32_t reserved74; /* ordinal251 */
uint32_t reserved75; /* ordinal252 */
uint32_t reserved76; /* ordinal253 */
uint32_t reserved77; /* ordinal254 */
uint32_t reserved78; /* ordinal255 */
uint32_t reserved_t[256]; /* Reserve 256 dword buffer used by ucode */
};
static void gfx_v8_0_cp_compute_fini(struct amdgpu_device *adev)
{
int i, r;
@ -4763,34 +4504,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
u32 *buf;
struct vi_mqd *mqd;
/* init the pipes */
mutex_lock(&adev->srbm_mutex);
for (i = 0; i < (adev->gfx.mec.num_pipe * adev->gfx.mec.num_mec); i++) {
int me = (i < 4) ? 1 : 2;
int pipe = (i < 4) ? i : (i - 4);
eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
eop_gpu_addr >>= 8;
vi_srbm_select(adev, me, pipe, 0, 0);
/* write the EOP addr */
WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
/* set the VMID assigned */
WREG32(mmCP_HQD_VMID, 0);
/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
tmp = RREG32(mmCP_HQD_EOP_CONTROL);
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
(order_base_2(MEC_HPD_SIZE / 4) - 1));
WREG32(mmCP_HQD_EOP_CONTROL, tmp);
}
vi_srbm_select(adev, 0, 0, 0, 0);
mutex_unlock(&adev->srbm_mutex);
/* init the queues. Just two for now. */
/* init the queues. */
for (i = 0; i < adev->gfx.num_compute_rings; i++) {
struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
@ -4842,6 +4556,22 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
ring->pipe,
ring->queue, 0);
eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + (i * MEC_HPD_SIZE);
eop_gpu_addr >>= 8;
/* write the EOP addr */
WREG32(mmCP_HQD_EOP_BASE_ADDR, eop_gpu_addr);
WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, upper_32_bits(eop_gpu_addr));
/* set the VMID assigned */
WREG32(mmCP_HQD_VMID, 0);
/* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
tmp = RREG32(mmCP_HQD_EOP_CONTROL);
tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
(order_base_2(MEC_HPD_SIZE / 4) - 1));
WREG32(mmCP_HQD_EOP_CONTROL, tmp);
/* disable wptr polling */
tmp = RREG32(mmCP_PQ_WPTR_POLL_CNTL);
tmp = REG_SET_FIELD(tmp, CP_PQ_WPTR_POLL_CNTL, EN, 0);
@ -4925,9 +4655,9 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
/* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
mqd->cp_hqd_pq_wptr_poll_addr = wb_gpu_addr & 0xfffffffc;
mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr);
WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR, mqd->cp_hqd_pq_wptr_poll_addr_lo);
WREG32(mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
mqd->cp_hqd_pq_wptr_poll_addr_hi);
@ -5098,6 +4828,10 @@ static int gfx_v8_0_hw_fini(void *handle)
amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
if (amdgpu_sriov_vf(adev)) {
pr_debug("For SRIOV client, shouldn't do anything.\n");
return 0;
}
gfx_v8_0_cp_enable(adev, false);
gfx_v8_0_rlc_stop(adev);
gfx_v8_0_cp_compute_fini(adev);
@ -5450,6 +5184,21 @@ static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_
return RREG32(mmSQ_IND_DATA);
}
static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
uint32_t wave, uint32_t thread,
uint32_t regno, uint32_t num, uint32_t *out)
{
WREG32(mmSQ_IND_INDEX,
(wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
(regno << SQ_IND_INDEX__INDEX__SHIFT) |
(thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
(SQ_IND_INDEX__FORCE_READ_MASK) |
(SQ_IND_INDEX__AUTO_INCR_MASK));
while (num--)
*(out++) = RREG32(mmSQ_IND_DATA);
}
static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
{
/* type 0 wave data */
@ -5474,11 +5223,21 @@ static void gfx_v8_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, u
dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
}
static void gfx_v8_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
uint32_t wave, uint32_t start,
uint32_t size, uint32_t *dst)
{
wave_read_regs(
adev, simd, wave, 0,
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
}
static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
.get_gpu_clock_counter = &gfx_v8_0_get_gpu_clock_counter,
.select_se_sh = &gfx_v8_0_select_se_sh,
.read_wave_data = &gfx_v8_0_read_wave_data,
.read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
};
static int gfx_v8_0_early_init(void *handle)
@ -5930,29 +5689,24 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
adev->gfx.rlc.funcs->enter_safe_mode(adev);
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
/* 1 enable cntx_empty_int_enable/cntx_busy_int_enable/
* Cmp_busy/GFX_Idle interrupts
*/
gfx_v8_0_enable_gui_idle_interrupt(adev, true);
temp1 = data1 = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
data1 &= ~RLC_CGTT_MGCG_OVERRIDE__CGCG_MASK;
if (temp1 != data1)
WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data1);
/* 2 wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
/* : wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
gfx_v8_0_wait_for_rlc_serdes(adev);
/* 3 - clear cgcg override */
/* 2 - clear cgcg override */
gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGCG_OVERRIDE, CLE_BPM_SERDES_CMD);
/* wait for RLC_SERDES_CU_MASTER & RLC_SERDES_NONCU_MASTER idle */
gfx_v8_0_wait_for_rlc_serdes(adev);
/* 4 - write cmd to set CGLS */
/* 3 - write cmd to set CGLS */
gfx_v8_0_send_serdes_cmd(adev, BPM_REG_CGLS_EN, SET_BPM_SERDES_CMD);
/* 5 - enable cgcg */
/* 4 - enable cgcg */
data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
@ -5970,6 +5724,11 @@ static void gfx_v8_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
if (temp != data)
WREG32(mmRLC_CGCG_CGLS_CTRL, data);
/* 5 enable cntx_empty_int_enable/cntx_busy_int_enable/
* Cmp_busy/GFX_Idle interrupts
*/
gfx_v8_0_enable_gui_idle_interrupt(adev, true);
} else {
/* disable cntx_empty_int_enable & GFX Idle interrupt */
gfx_v8_0_enable_gui_idle_interrupt(adev, false);

7
drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
View File

@ -335,7 +335,7 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev)
* size equal to the 1024 or vram, whichever is larger.
*/
if (amdgpu_gart_size == -1)
adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);
adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
else
adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
@ -795,11 +795,6 @@ static int gmc_v6_0_sw_init(void *handle)
return r;
}
r = amdgpu_ttm_global_init(adev);
if (r) {
return r;
}
r = gmc_v6_0_mc_init(adev);
if (r)
return r;

7
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
View File

@ -385,7 +385,7 @@ static int gmc_v7_0_mc_init(struct amdgpu_device *adev)
* size equal to the 1024 or vram, whichever is larger.
*/
if (amdgpu_gart_size == -1)
adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);
adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
else
adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
@ -945,11 +945,6 @@ static int gmc_v7_0_sw_init(void *handle)
return r;
}
r = amdgpu_ttm_global_init(adev);
if (r) {
return r;
}
r = gmc_v7_0_mc_init(adev);
if (r)
return r;

7
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
View File

@ -472,7 +472,7 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev)
* size equal to the 1024 or vram, whichever is larger.
*/
if (amdgpu_gart_size == -1)
adev->mc.gtt_size = amdgpu_ttm_get_gtt_mem_size(adev);
adev->mc.gtt_size = max((1024ULL << 20), adev->mc.mc_vram_size);
else
adev->mc.gtt_size = (uint64_t)amdgpu_gart_size << 20;
@ -952,11 +952,6 @@ static int gmc_v8_0_sw_init(void *handle)
return r;
}
r = amdgpu_ttm_global_init(adev);
if (r) {
return r;
}
r = gmc_v8_0_mc_init(adev);
if (r)
return r;

2
drivers/gpu/drm/amd/amdgpu/si_dpm.c
View File

@ -3506,6 +3506,7 @@ static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
(adev->pdev->revision == 0x80) ||
(adev->pdev->revision == 0x81) ||
(adev->pdev->revision == 0x83) ||
(adev->pdev->revision == 0x87) ||
(adev->pdev->device == 0x6604) ||
(adev->pdev->device == 0x6605)) {
max_sclk = 75000;
@ -7715,6 +7716,7 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev)
(adev->pdev->revision == 0x80) ||
(adev->pdev->revision == 0x81) ||
(adev->pdev->revision == 0x83) ||
(adev->pdev->revision == 0x87) ||
(adev->pdev->device == 0x6604) ||
(adev->pdev->device == 0x6605))
chip_name = "oland_k";

6
drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
View File

@ -640,7 +640,7 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
UVD_SUVD_CGC_GATE__SDB_MASK;
if (enable) {
data3 |= (UVD_CGC_GATE__SYS_MASK |
data3 |= (UVD_CGC_GATE__SYS_MASK |
UVD_CGC_GATE__UDEC_MASK |
UVD_CGC_GATE__MPEG2_MASK |
UVD_CGC_GATE__RBC_MASK |
@ -656,9 +656,11 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
UVD_CGC_GATE__UDEC_DB_MASK |
UVD_CGC_GATE__UDEC_MP_MASK |
UVD_CGC_GATE__WCB_MASK |
UVD_CGC_GATE__VCPU_MASK |
UVD_CGC_GATE__JPEG_MASK |
UVD_CGC_GATE__SCPU_MASK);
/* only in pg enabled, we can gate clock to vcpu*/
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
data3 |= UVD_CGC_GATE__VCPU_MASK;
data3 &= ~UVD_CGC_GATE__REGS_MASK;
data1 |= suvd_flags;
} else {

115
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
View File

@ -42,6 +42,10 @@ static void uvd_v6_0_set_irq_funcs(struct amdgpu_device *adev);
static int uvd_v6_0_start(struct amdgpu_device *adev);
static void uvd_v6_0_stop(struct amdgpu_device *adev);
static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev);
static int uvd_v6_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state);
static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
bool enable);
/**
* uvd_v6_0_ring_get_rptr - get read pointer
@ -151,8 +155,6 @@ static int uvd_v6_0_hw_init(void *handle)
uint32_t tmp;
int r;
amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
r = uvd_v6_0_start(adev);
if (r)
goto done;
@ -395,11 +397,11 @@ static int uvd_v6_0_start(struct amdgpu_device *adev)
lmi_swap_cntl = 0;
mp_swap_cntl = 0;
amdgpu_asic_set_uvd_clocks(adev, 10000, 10000);
uvd_v6_0_set_clockgating_state(adev, AMD_CG_STATE_UNGATE);
uvd_v6_0_enable_mgcg(adev, true);
uvd_v6_0_mc_resume(adev);
/* disable clock gating */
WREG32_FIELD(UVD_CGC_CTRL, DYN_CLOCK_MODE, 0);
/* disable interupt */
WREG32_FIELD(UVD_MASTINT_EN, VCPU_EN, 0);
@ -838,22 +840,72 @@ static int uvd_v6_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable)
{
uint32_t data1, data3;
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
data3 = RREG32(mmUVD_CGC_GATE);
data1 |= UVD_SUVD_CGC_GATE__SRE_MASK |
UVD_SUVD_CGC_GATE__SIT_MASK |
UVD_SUVD_CGC_GATE__SMP_MASK |
UVD_SUVD_CGC_GATE__SCM_MASK |
UVD_SUVD_CGC_GATE__SDB_MASK |
UVD_SUVD_CGC_GATE__SRE_H264_MASK |
UVD_SUVD_CGC_GATE__SRE_HEVC_MASK |
UVD_SUVD_CGC_GATE__SIT_H264_MASK |
UVD_SUVD_CGC_GATE__SIT_HEVC_MASK |
UVD_SUVD_CGC_GATE__SCM_H264_MASK |
UVD_SUVD_CGC_GATE__SCM_HEVC_MASK |
UVD_SUVD_CGC_GATE__SDB_H264_MASK |
UVD_SUVD_CGC_GATE__SDB_HEVC_MASK;
if (enable) {
data3 |= (UVD_CGC_GATE__SYS_MASK |
UVD_CGC_GATE__UDEC_MASK |
UVD_CGC_GATE__MPEG2_MASK |
UVD_CGC_GATE__RBC_MASK |
UVD_CGC_GATE__LMI_MC_MASK |
UVD_CGC_GATE__LMI_UMC_MASK |
UVD_CGC_GATE__IDCT_MASK |
UVD_CGC_GATE__MPRD_MASK |
UVD_CGC_GATE__MPC_MASK |
UVD_CGC_GATE__LBSI_MASK |
UVD_CGC_GATE__LRBBM_MASK |
UVD_CGC_GATE__UDEC_RE_MASK |
UVD_CGC_GATE__UDEC_CM_MASK |
UVD_CGC_GATE__UDEC_IT_MASK |
UVD_CGC_GATE__UDEC_DB_MASK |
UVD_CGC_GATE__UDEC_MP_MASK |
UVD_CGC_GATE__WCB_MASK |
UVD_CGC_GATE__JPEG_MASK |
UVD_CGC_GATE__SCPU_MASK |
UVD_CGC_GATE__JPEG2_MASK);
/* only in pg enabled, we can gate clock to vcpu*/
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
data3 |= UVD_CGC_GATE__VCPU_MASK;
data3 &= ~UVD_CGC_GATE__REGS_MASK;
} else {
data3 = 0;
}
WREG32(mmUVD_SUVD_CGC_GATE, data1);
WREG32(mmUVD_CGC_GATE, data3);
}
static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
{
uint32_t data, data1, data2, suvd_flags;
uint32_t data, data2;
data = RREG32(mmUVD_CGC_CTRL);
data1 = RREG32(mmUVD_SUVD_CGC_GATE);
data2 = RREG32(mmUVD_SUVD_CGC_CTRL);
data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
UVD_SUVD_CGC_GATE__SIT_MASK |
UVD_SUVD_CGC_GATE__SMP_MASK |
UVD_SUVD_CGC_GATE__SCM_MASK |
UVD_SUVD_CGC_GATE__SDB_MASK;
data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
(1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
@ -886,11 +938,8 @@ static void uvd_v6_0_set_sw_clock_gating(struct amdgpu_device *adev)
UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
data1 |= suvd_flags;
WREG32(mmUVD_CGC_CTRL, data);
WREG32(mmUVD_CGC_GATE, 0);
WREG32(mmUVD_SUVD_CGC_GATE, data1);
WREG32(mmUVD_SUVD_CGC_CTRL, data2);
}
@ -937,6 +986,32 @@ static void uvd_v6_0_set_hw_clock_gating(struct amdgpu_device *adev)
}
#endif
static void uvd_v6_0_enable_mgcg(struct amdgpu_device *adev,
bool enable)
{
u32 orig, data;
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG)) {
data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
data |= 0xfff;
WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
orig = data = RREG32(mmUVD_CGC_CTRL);
data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
if (orig != data)
WREG32(mmUVD_CGC_CTRL, data);
} else {
data = RREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL);
data &= ~0xfff;
WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data);
orig = data = RREG32(mmUVD_CGC_CTRL);
data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
if (orig != data)
WREG32(mmUVD_CGC_CTRL, data);
}
}
static int uvd_v6_0_set_clockgating_state(void *handle,
enum amd_clockgating_state state)
{
@ -947,17 +1022,17 @@ static int uvd_v6_0_set_clockgating_state(void *handle,
return 0;
if (enable) {
/* disable HW gating and enable Sw gating */
uvd_v6_0_set_sw_clock_gating(adev);
} else {
/* wait for STATUS to clear */
if (uvd_v6_0_wait_for_idle(handle))
return -EBUSY;
uvd_v6_0_enable_clock_gating(adev, true);
/* enable HW gates because UVD is idle */
/* uvd_v6_0_set_hw_clock_gating(adev); */
} else {
/* disable HW gating and enable Sw gating */
uvd_v6_0_enable_clock_gating(adev, false);
}
uvd_v6_0_set_sw_clock_gating(adev);
return 0;
}

2
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
View File

@ -134,7 +134,7 @@ static void vce_v3_0_set_vce_sw_clock_gating(struct amdgpu_device *adev,
accessible but the firmware will throttle the clocks on the
fly as necessary.
*/
if (gated) {
if (!gated) {
data = RREG32(mmVCE_CLOCK_GATING_B);
data |= 0x1ff;
data &= ~0xef0000;

6
drivers/gpu/drm/amd/amdgpu/vi.c
View File

@ -937,12 +937,14 @@ static int vi_common_early_init(void *handle)
adev->external_rev_id = adev->rev_id + 0x14;
break;
case CHIP_POLARIS11:
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_VCE_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x5A;
break;
case CHIP_POLARIS10:
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
AMD_CG_SUPPORT_VCE_MGCG;
adev->pg_flags = 0;
adev->external_rev_id = adev->rev_id + 0x50;
break;

4
drivers/gpu/drm/amd/powerplay/amd_powerplay.c
View File

@ -1004,12 +1004,12 @@ int amd_powerplay_reset(void *handle)
if (ret)
return ret;
hw_init_power_state_table(instance->hwmgr);
if ((amdgpu_dpm == 0)
|| cgs_is_virtualization_enabled(instance->smu_mgr->device))
return 0;
hw_init_power_state_table(instance->hwmgr);
if (eventmgr == NULL || eventmgr->pp_eventmgr_init == NULL)
return -EINVAL;

2
drivers/gpu/drm/amd/powerplay/eventmgr/eventtasks.c
View File

@ -154,7 +154,7 @@ int pem_task_powerdown_vce_tasks(struct pp_eventmgr *eventmgr, struct pem_event_
int pem_task_disable_clock_power_gatings_tasks(struct pp_eventmgr *eventmgr, struct pem_event_data *event_data)
{
/* TODO */
phm_disable_clock_power_gatings(eventmgr->hwmgr);
return 0;
}

2
drivers/gpu/drm/amd/powerplay/hwmgr/functiontables.c
View File

@ -35,7 +35,7 @@ static int phm_run_table(struct pp_hwmgr *hwmgr,
phm_table_function *function;
if (rt_table->function_list == NULL) {
printk(KERN_INFO "[ powerplay ] this function not implement!\n");
pr_debug("[ powerplay ] this function not implement!\n");
return 0;
}

13
drivers/gpu/drm/amd/powerplay/hwmgr/hardwaremanager.c
View File

@ -209,6 +209,19 @@ int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr)
return 0;
}
int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr)
{
PHM_FUNC_CHECK(hwmgr);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_TablelessHardwareInterface)) {
if (NULL != hwmgr->hwmgr_func->disable_clock_power_gating)
return hwmgr->hwmgr_func->disable_clock_power_gating(hwmgr);
}
return 0;
}
int phm_display_configuration_changed(struct pp_hwmgr *hwmgr)
{
PHM_FUNC_CHECK(hwmgr);

1
drivers/gpu/drm/amd/powerplay/inc/hardwaremanager.h
View File

@ -334,6 +334,7 @@ struct phm_clocks {
uint32_t clock[MAX_NUM_CLOCKS];
};
extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);

6
drivers/gpu/drm/amd/powerplay/smumgr/fiji_smc.c
View File

@ -1958,6 +1958,12 @@ int fiji_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
int res;
uint64_t tmp64;
if (hwmgr->thermal_controller.fanInfo.bNoFan) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);
return 0;
}
if (smu_data->smu7_data.fan_table_start == 0) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);

6
drivers/gpu/drm/amd/powerplay/smumgr/iceland_smc.c
View File

@ -2006,6 +2006,12 @@ int iceland_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl))
return 0;
if (hwmgr->thermal_controller.fanInfo.bNoFan) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);
return 0;
}
if (0 == smu7_data->fan_table_start) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl);
return 0;

6
drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smc.c
View File

@ -1885,6 +1885,12 @@ int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
int res;
uint64_t tmp64;
if (hwmgr->thermal_controller.fanInfo.bNoFan) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);
return 0;
}
if (smu_data->smu7_data.fan_table_start == 0) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);

21
drivers/gpu/drm/amd/powerplay/smumgr/smu7_smumgr.c
View File

@ -366,12 +366,16 @@ static int smu7_populate_single_firmware_entry(struct pp_smumgr *smumgr,
&info);
if (!result) {
entry->version = info.version;
entry->version = info.fw_version;
entry->id = (uint16_t)fw_type;
entry->image_addr_high = smu_upper_32_bits(info.mc_addr);
entry->image_addr_low = smu_lower_32_bits(info.mc_addr);
entry->meta_data_addr_high = 0;
entry->meta_data_addr_low = 0;
/* digest need be excluded out */
if (cgs_is_virtualization_enabled(smumgr->device))
info.image_size -= 20;
entry->data_size_byte = info.image_size;
entry->num_register_entries = 0;
}
@ -403,8 +407,14 @@ int smu7_request_smu_load_fw(struct pp_smumgr *smumgr)
0x0);
if (smumgr->chip_id > CHIP_TOPAZ) { /* add support for Topaz */
smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high);
smu7_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low);
if (!cgs_is_virtualization_enabled(smumgr->device)) {
smu7_send_msg_to_smc_with_parameter(smumgr,
PPSMC_MSG_SMU_DRAM_ADDR_HI,
smu_data->smu_buffer.mc_addr_high);
smu7_send_msg_to_smc_with_parameter(smumgr,
PPSMC_MSG_SMU_DRAM_ADDR_LO,
smu_data->smu_buffer.mc_addr_low);
}
fw_to_load = UCODE_ID_RLC_G_MASK
+ UCODE_ID_SDMA0_MASK
+ UCODE_ID_SDMA1_MASK
@ -539,7 +549,6 @@ int smu7_init(struct pp_smumgr *smumgr)
smu_data = (struct smu7_smumgr *)(smumgr->backend);
smu_data->header_buffer.data_size =
((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096;
smu_data->smu_buffer.data_size = 200*4096;
/* Allocate FW image data structure and header buffer and
* send the header buffer address to SMU */
@ -562,6 +571,10 @@ int smu7_init(struct pp_smumgr *smumgr)
(cgs_handle_t)smu_data->header_buffer.handle);
return -EINVAL);
if (cgs_is_virtualization_enabled(smumgr->device))
return 0;
smu_data->smu_buffer.data_size = 200*4096;
smu_allocate_memory(smumgr->device,
smu_data->smu_buffer.data_size,
CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB,

6
drivers/gpu/drm/amd/powerplay/smumgr/tonga_smc.c
View File

@ -2496,6 +2496,12 @@ int tonga_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
PHM_PlatformCaps_MicrocodeFanControl))
return 0;
if (hwmgr->thermal_controller.fanInfo.bNoFan) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);
return 0;
}
if (0 == smu_data->smu7_data.fan_table_start) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MicrocodeFanControl);

73
drivers/gpu/drm/radeon/radeon_cursor.c
View File

@ -90,6 +90,9 @@ static void radeon_show_cursor(struct drm_crtc *crtc)
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
struct radeon_device *rdev = crtc->dev->dev_private;
if (radeon_crtc->cursor_out_of_bounds)
return;
if (ASIC_IS_DCE4(rdev)) {
WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
upper_32_bits(radeon_crtc->cursor_addr));
@ -143,21 +146,25 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
int xorigin = 0, yorigin = 0;
int w = radeon_crtc->cursor_width;
radeon_crtc->cursor_x = x;
radeon_crtc->cursor_y = y;
if (ASIC_IS_AVIVO(rdev)) {
/* avivo cursor are offset into the total surface */
x += crtc->x;
y += crtc->y;
}
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
if (x < 0) {
if (x < 0)
xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
x = 0;
}
if (y < 0) {
if (y < 0)
yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
y = 0;
if (!ASIC_IS_AVIVO(rdev)) {
x += crtc->x;
y += crtc->y;
}
DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
/* fixed on DCE6 and newer */
if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
@ -180,27 +187,31 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
if (i > 1) {
int cursor_end, frame_end;
cursor_end = x - xorigin + w;
cursor_end = x + w;
frame_end = crtc->x + crtc->mode.crtc_hdisplay;
if (cursor_end >= frame_end) {
w = w - (cursor_end - frame_end);
if (!(frame_end & 0x7f))
w--;
} else {
if (!(cursor_end & 0x7f))
w--;
} else if (cursor_end <= 0) {
goto out_of_bounds;
} else if (!(cursor_end & 0x7f)) {
w--;
}
if (w <= 0) {
w = 1;
cursor_end = x - xorigin + w;
if (!(cursor_end & 0x7f)) {
x--;
WARN_ON_ONCE(x < 0);
}
goto out_of_bounds;
}
}
}
if (x <= (crtc->x - w) || y <= (crtc->y - radeon_crtc->cursor_height) ||
x >= (crtc->x + crtc->mode.crtc_hdisplay) ||
y >= (crtc->y + crtc->mode.crtc_vdisplay))
goto out_of_bounds;
x += xorigin;
y += yorigin;
if (ASIC_IS_DCE4(rdev)) {
WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
@ -212,6 +223,9 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
} else {
x -= crtc->x;
y -= crtc->y;
if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
y *= 2;
@ -229,10 +243,20 @@ static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
yorigin * 256);
}
radeon_crtc->cursor_x = x;
radeon_crtc->cursor_y = y;
if (radeon_crtc->cursor_out_of_bounds) {
radeon_crtc->cursor_out_of_bounds = false;
if (radeon_crtc->cursor_bo)
radeon_show_cursor(crtc);
}
return 0;
out_of_bounds:
if (!radeon_crtc->cursor_out_of_bounds) {
radeon_hide_cursor(crtc);
radeon_crtc->cursor_out_of_bounds = true;
}
return 0;
}
int radeon_crtc_cursor_move(struct drm_crtc *crtc,
@ -297,22 +321,23 @@ int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
return ret;
}
radeon_crtc->cursor_width = width;
radeon_crtc->cursor_height = height;
radeon_lock_cursor(crtc, true);
if (hot_x != radeon_crtc->cursor_hot_x ||
if (width != radeon_crtc->cursor_width ||
height != radeon_crtc->cursor_height ||
hot_x != radeon_crtc->cursor_hot_x ||
hot_y != radeon_crtc->cursor_hot_y) {
int x, y;
x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;
y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;
radeon_cursor_move_locked(crtc, x, y);
radeon_crtc->cursor_width = width;
radeon_crtc->cursor_height = height;
radeon_crtc->cursor_hot_x = hot_x;
radeon_crtc->cursor_hot_y = hot_y;
radeon_cursor_move_locked(crtc, x, y);
}
radeon_show_cursor(crtc);

1
drivers/gpu/drm/radeon/radeon_mode.h
View File

@ -330,6 +330,7 @@ struct radeon_crtc {
u16 lut_r[256], lut_g[256], lut_b[256];
bool enabled;
bool can_tile;
bool cursor_out_of_bounds;
uint32_t crtc_offset;
struct drm_gem_object *cursor_bo;
uint64_t cursor_addr;

1
drivers/gpu/drm/radeon/si.c
View File

@ -1714,6 +1714,7 @@ static int si_init_microcode(struct radeon_device *rdev)
(rdev->pdev->revision == 0x80) ||
(rdev->pdev->revision == 0x81) ||
(rdev->pdev->revision == 0x83) ||
(rdev->pdev->revision == 0x87) ||
(rdev->pdev->device == 0x6604) ||
(rdev->pdev->device == 0x6605))
new_smc = true;

1
drivers/gpu/drm/radeon/si_dpm.c
View File

@ -3026,6 +3026,7 @@ static void si_apply_state_adjust_rules(struct radeon_device *rdev,
(rdev->pdev->revision == 0x80) ||
(rdev->pdev->revision == 0x81) ||
(rdev->pdev->revision == 0x83) ||
(rdev->pdev->revision == 0x87) ||
(rdev->pdev->device == 0x6604) ||
(rdev->pdev->device == 0x6605)) {
max_sclk = 75000;

11
include/uapi/drm/amdgpu_drm.h
View File

@ -522,6 +522,12 @@ struct drm_amdgpu_cs_chunk_data {
#define AMDGPU_INFO_MEMORY 0x19
/* Query vce clock table */
#define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
/* Query vbios related information */
#define AMDGPU_INFO_VBIOS 0x1B
/* Subquery id: Query vbios size */
#define AMDGPU_INFO_VBIOS_SIZE 0x1
/* Subquery id: Query vbios image */
#define AMDGPU_INFO_VBIOS_IMAGE 0x2
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
@ -580,6 +586,11 @@ struct drm_amdgpu_info {
} read_mmr_reg;
struct drm_amdgpu_query_fw query_fw;
struct {
__u32 type;
__u32 offset;
} vbios_info;
};
};