ARM: dts: stm32: add timers support on stm32mp131
Add timers support to STM32MP13x SoC family. Signed-off-by: Olivier Moysan <olivier.moysan@foss.st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
Olivier Moysan
Alexandre Torgue
parent
0a5afd3ee0
commit
bf9d876bea
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@ -119,6 +119,221 @@
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};
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};
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timers2: timer@40000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM2_K>;
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clock-names = "int";
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dmas = <&dmamux1 18 0x400 0x1>,
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<&dmamux1 19 0x400 0x1>,
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<&dmamux1 20 0x400 0x1>,
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<&dmamux1 21 0x400 0x1>,
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<&dmamux1 22 0x400 0x1>;
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dma-names = "ch1", "ch2", "ch3", "ch4", "up";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@1 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <1>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers3: timer@40001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM3_K>;
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clock-names = "int";
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dmas = <&dmamux1 23 0x400 0x1>,
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<&dmamux1 24 0x400 0x1>,
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<&dmamux1 25 0x400 0x1>,
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<&dmamux1 26 0x400 0x1>,
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<&dmamux1 27 0x400 0x1>,
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<&dmamux1 28 0x400 0x1>;
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dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@2 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <2>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers4: timer@40002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM4_K>;
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clock-names = "int";
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dmas = <&dmamux1 29 0x400 0x1>,
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<&dmamux1 30 0x400 0x1>,
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<&dmamux1 31 0x400 0x1>,
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<&dmamux1 32 0x400 0x1>;
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dma-names = "ch1", "ch2", "ch3", "up";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@3 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <3>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers5: timer@40003000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40003000 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM5_K>;
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clock-names = "int";
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dmas = <&dmamux1 55 0x400 0x1>,
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<&dmamux1 56 0x400 0x1>,
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<&dmamux1 57 0x400 0x1>,
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<&dmamux1 58 0x400 0x1>,
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<&dmamux1 59 0x400 0x1>,
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<&dmamux1 60 0x400 0x1>;
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dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@4 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <4>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers6: timer@40004000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40004000 0x400>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM6_K>;
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clock-names = "int";
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dmas = <&dmamux1 69 0x400 0x1>;
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dma-names = "up";
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status = "disabled";
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timer@5 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <5>;
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status = "disabled";
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};
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};
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timers7: timer@40005000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40005000 0x400>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM7_K>;
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clock-names = "int";
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dmas = <&dmamux1 70 0x400 0x1>;
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dma-names = "up";
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status = "disabled";
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timer@6 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <6>;
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status = "disabled";
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};
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};
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lptimer1: timer@40009000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x40009000 0x400>;
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interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc LPTIM1_K>;
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clock-names = "mux";
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wakeup-source;
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm-lp";
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#pwm-cells = <3>;
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status = "disabled";
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};
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trigger@0 {
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compatible = "st,stm32-lptimer-trigger";
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reg = <0>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-lptimer-counter";
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status = "disabled";
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};
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timer {
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compatible = "st,stm32-lptimer-timer";
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status = "disabled";
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};
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};
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i2s2: audio-controller@4000b000 {
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compatible = "st,stm32h7-i2s";
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reg = <0x4000b000 0x400>;
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@ -227,6 +442,88 @@
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status = "disabled";
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};
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timers1: timer@44000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44000000 0x400>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "brk", "up", "trg-com", "cc";
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clocks = <&rcc TIM1_K>;
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clock-names = "int";
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dmas = <&dmamux1 11 0x400 0x1>,
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<&dmamux1 12 0x400 0x1>,
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<&dmamux1 13 0x400 0x1>,
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<&dmamux1 14 0x400 0x1>,
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<&dmamux1 15 0x400 0x1>,
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<&dmamux1 16 0x400 0x1>,
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<&dmamux1 17 0x400 0x1>;
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dma-names = "ch1", "ch2", "ch3", "ch4",
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"up", "trig", "com";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@0 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <0>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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timers8: timer@44001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x44001000 0x400>;
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interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "brk", "up", "trg-com", "cc";
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clocks = <&rcc TIM8_K>;
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clock-names = "int";
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dmas = <&dmamux1 47 0x400 0x1>,
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<&dmamux1 48 0x400 0x1>,
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<&dmamux1 49 0x400 0x1>,
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<&dmamux1 50 0x400 0x1>,
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<&dmamux1 51 0x400 0x1>,
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<&dmamux1 52 0x400 0x1>,
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<&dmamux1 53 0x400 0x1>;
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dma-names = "ch1", "ch2", "ch3", "ch4",
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"up", "trig", "com";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@7 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <7>;
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status = "disabled";
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};
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counter {
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compatible = "st,stm32-timer-counter";
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status = "disabled";
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};
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};
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i2s1: audio-controller@44004000 {
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compatible = "st,stm32h7-i2s";
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reg = <0x44004000 0x400>;
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@ -544,6 +841,161 @@
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status = "disabled";
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};
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timers12: timer@4c007000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x4c007000 0x400>;
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interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM12_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@11 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <11>;
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status = "disabled";
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};
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};
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timers13: timer@4c008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x4c008000 0x400>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM13_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@12 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <12>;
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status = "disabled";
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};
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};
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timers14: timer@4c009000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x4c009000 0x400>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM14_K>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@13 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <13>;
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status = "disabled";
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};
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};
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timers15: timer@4c00a000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x4c00a000 0x400>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM15_K>;
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clock-names = "int";
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dmas = <&dmamux1 105 0x400 0x1>,
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<&dmamux1 106 0x400 0x1>,
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<&dmamux1 107 0x400 0x1>,
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<&dmamux1 108 0x400 0x1>;
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dma-names = "ch1", "up", "trig", "com";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@14 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <14>;
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status = "disabled";
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};
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};
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timers16: timer@4c00b000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x4c00b000 0x400>;
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interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM16_K>;
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clock-names = "int";
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dmas = <&dmamux1 109 0x400 0x1>,
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<&dmamux1 110 0x400 0x1>;
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dma-names = "ch1", "up";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@15 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <15>;
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status = "disabled";
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};
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};
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timers17: timer@4c00c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x4c00c000 0x400>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "global";
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clocks = <&rcc TIM17_K>;
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clock-names = "int";
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dmas = <&dmamux1 111 0x400 0x1>,
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<&dmamux1 112 0x400 0x1>;
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dma-names = "ch1", "up";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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#pwm-cells = <3>;
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status = "disabled";
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};
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timer@16 {
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compatible = "st,stm32h7-timer-trigger";
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reg = <16>;
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status = "disabled";
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};
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};
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rcc: rcc@50000000 {
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compatible = "st,stm32mp13-rcc", "syscon";
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reg = <0x50000000 0x1000>;
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@ -570,6 +1022,111 @@
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clocks = <&rcc SYSCFG>;
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};
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lptimer2: timer@50021000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-lptimer";
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reg = <0x50021000 0x400>;
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interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc LPTIM2_K>;
|
||||
clock-names = "mux";
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trigger@1 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-lptimer-counter";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "st,stm32-lptimer-timer";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer3: timer@50022000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x50022000 0x400>;
|
||||
interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc LPTIM3_K>;
|
||||
clock-names = "mux";
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trigger@2 {
|
||||
compatible = "st,stm32-lptimer-trigger";
|
||||
reg = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "st,stm32-lptimer-timer";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer4: timer@50023000 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x50023000 0x400>;
|
||||
interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc LPTIM4_K>;
|
||||
clock-names = "mux";
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "st,stm32-lptimer-timer";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
lptimer5: timer@50024000 {
|
||||
compatible = "st,stm32-lptimer";
|
||||
reg = <0x50024000 0x400>;
|
||||
interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&rcc LPTIM5_K>;
|
||||
clock-names = "mux";
|
||||
wakeup-source;
|
||||
status = "disabled";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm-lp";
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "st,stm32-lptimer-timer";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
mdma: dma-controller@58000000 {
|
||||
compatible = "st,stm32h7-mdma";
|
||||
reg = <0x58000000 0x1000>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue