drm/amdgpu: introduce new amdgpu_fence object to indicate the job embedded fence
The job embedded fence donesn't initialize the flags at dma_fence_init(). Then we will go a wrong way in amdgpu_fence_get_timeline_name callback and trigger a null pointer panic once we enabled the trace event here. So introduce new amdgpu_fence object to indicate the job embedded fence. [ 156.131790] BUG: kernel NULL pointer dereference, address: 00000000000002a0 [ 156.131804] #PF: supervisor read access in kernel mode [ 156.131811] #PF: error_code(0x0000) - not-present page [ 156.131817] PGD 0 P4D 0 [ 156.131824] Oops: 0000 [#1] PREEMPT SMP PTI [ 156.131832] CPU: 6 PID: 1404 Comm: sdma0 Tainted: G OE 5.16.0-rc1-custom #1 [ 156.131842] Hardware name: Gigabyte Technology Co., Ltd. Z170XP-SLI/Z170XP-SLI-CF, BIOS F20 11/04/2016 [ 156.131848] RIP: 0010:strlen+0x0/0x20 [ 156.131859] Code: 89 c0 c3 0f 1f 80 00 00 00 00 48 01 fe eb 0f 0f b6 07 38 d0 74 10 48 83 c7 01 84 c0 74 05 48 39 f7 75 ec 31 c0 c3 48 89 f8 c3 <80> 3f 00 74 10 48 89 f8 48 83 c0 01 80 38 00 75 f7 48 29 f8 c3 31 [ 156.131872] RSP: 0018:ffff9bd0018dbcf8 EFLAGS: 00010206 [ 156.131880] RAX: 00000000000002a0 RBX: ffff8d0305ef01b0 RCX: 000000000000000b [ 156.131888] RDX: ffff8d03772ab924 RSI: ffff8d0305ef01b0 RDI: 00000000000002a0 [ 156.131895] RBP: ffff9bd0018dbd60 R08: ffff8d03002094d0 R09: 0000000000000000 [ 156.131901] R10: 000000000000005e R11: 0000000000000065 R12: ffff8d03002094d0 [ 156.131907] R13: 000000000000001f R14: 0000000000070018 R15: 0000000000000007 [ 156.131914] FS: 0000000000000000(0000) GS:ffff8d062ed80000(0000) knlGS:0000000000000000 [ 156.131923] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 156.131929] CR2: 00000000000002a0 CR3: 000000001120a005 CR4: 00000000003706e0 [ 156.131937] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 156.131942] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 156.131949] Call Trace: [ 156.131953] <TASK> [ 156.131957] ? trace_event_raw_event_dma_fence+0xcc/0x200 [ 156.131973] ? ring_buffer_unlock_commit+0x23/0x130 [ 156.131982] dma_fence_init+0x92/0xb0 [ 156.131993] amdgpu_fence_emit+0x10d/0x2b0 [amdgpu] [ 156.132302] amdgpu_ib_schedule+0x2f9/0x580 [amdgpu] [ 156.132586] amdgpu_job_run+0xed/0x220 [amdgpu] v2: fix mismatch warning between the prototype and function name (Ray, kernel test robot) Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -4461,7 +4461,7 @@ int amdgpu_device_mode1_reset(struct amdgpu_device *adev)
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int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
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struct amdgpu_reset_context *reset_context)
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{
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int i, j, r = 0;
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int i, r = 0;
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struct amdgpu_job *job = NULL;
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bool need_full_reset =
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test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags);
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@ -4483,15 +4483,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,
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/*clear job fence from fence drv to avoid force_completion
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*leave NULL and vm flush fence in fence drv */
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for (j = 0; j <= ring->fence_drv.num_fences_mask; j++) {
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struct dma_fence *old, **ptr;
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amdgpu_fence_driver_clear_job_fences(ring);
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ptr = &ring->fence_drv.fences[j];
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old = rcu_dereference_protected(*ptr, 1);
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if (old && test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &old->flags)) {
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RCU_INIT_POINTER(*ptr, NULL);
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}
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}
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/* after all hw jobs are reset, hw fence is meaningless, so force_completion */
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amdgpu_fence_driver_force_completion(ring);
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}
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@ -77,11 +77,13 @@ void amdgpu_fence_slab_fini(void)
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* Cast helper
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*/
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static const struct dma_fence_ops amdgpu_fence_ops;
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static const struct dma_fence_ops amdgpu_job_fence_ops;
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static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
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{
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struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
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if (__f->base.ops == &amdgpu_fence_ops)
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if (__f->base.ops == &amdgpu_fence_ops ||
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__f->base.ops == &amdgpu_job_fence_ops)
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return __f;
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return NULL;
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@ -158,19 +160,18 @@ int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amd
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}
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seq = ++ring->fence_drv.sync_seq;
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if (job != NULL && job->job_run_counter) {
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if (job && job->job_run_counter) {
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/* reinit seq for resubmitted jobs */
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fence->seqno = seq;
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} else {
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dma_fence_init(fence, &amdgpu_fence_ops,
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&ring->fence_drv.lock,
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adev->fence_context + ring->idx,
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seq);
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}
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if (job != NULL) {
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/* mark this fence has a parent job */
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set_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &fence->flags);
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if (job)
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dma_fence_init(fence, &amdgpu_job_fence_ops,
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&ring->fence_drv.lock,
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adev->fence_context + ring->idx, seq);
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else
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dma_fence_init(fence, &amdgpu_fence_ops,
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&ring->fence_drv.lock,
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adev->fence_context + ring->idx, seq);
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}
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amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
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@ -620,6 +621,25 @@ void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
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}
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}
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/**
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* amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring
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*
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* @ring: fence of the ring to be cleared
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*
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*/
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void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
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{
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int i;
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struct dma_fence *old, **ptr;
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for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
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ptr = &ring->fence_drv.fences[i];
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old = rcu_dereference_protected(*ptr, 1);
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if (old && old->ops == &amdgpu_job_fence_ops)
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RCU_INIT_POINTER(*ptr, NULL);
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}
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}
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/**
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* amdgpu_fence_driver_force_completion - force signal latest fence of ring
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*
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@ -643,16 +663,14 @@ static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
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static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
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{
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struct amdgpu_ring *ring;
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return (const char *)to_amdgpu_fence(f)->ring->name;
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}
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if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
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struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
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static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
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{
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struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
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ring = to_amdgpu_ring(job->base.sched);
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} else {
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ring = to_amdgpu_fence(f)->ring;
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}
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return (const char *)ring->name;
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return (const char *)to_amdgpu_ring(job->base.sched)->name;
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}
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/**
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@ -665,18 +683,25 @@ static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
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*/
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static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
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{
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struct amdgpu_ring *ring;
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if (!timer_pending(&to_amdgpu_fence(f)->ring->fence_drv.fallback_timer))
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amdgpu_fence_schedule_fallback(to_amdgpu_fence(f)->ring);
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if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
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struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
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return true;
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}
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ring = to_amdgpu_ring(job->base.sched);
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} else {
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ring = to_amdgpu_fence(f)->ring;
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}
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/**
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* amdgpu_job_fence_enable_signaling - enable signalling on job fence
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* @f: fence
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*
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* This is the simliar function with amdgpu_fence_enable_signaling above, it
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* only handles the job embedded fence.
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*/
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static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
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{
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struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
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if (!timer_pending(&ring->fence_drv.fallback_timer))
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amdgpu_fence_schedule_fallback(ring);
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if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
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amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
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return true;
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}
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@ -692,19 +717,23 @@ static void amdgpu_fence_free(struct rcu_head *rcu)
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{
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struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
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if (test_bit(AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT, &f->flags)) {
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/* free job if fence has a parent job */
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struct amdgpu_job *job;
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job = container_of(f, struct amdgpu_job, hw_fence);
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kfree(job);
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} else {
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/* free fence_slab if it's separated fence*/
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struct amdgpu_fence *fence;
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kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));
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}
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fence = to_amdgpu_fence(f);
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kmem_cache_free(amdgpu_fence_slab, fence);
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}
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/**
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* amdgpu_job_fence_free - free up the job with embedded fence
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*
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* @rcu: RCU callback head
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*
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* Free up the job with embedded fence after the RCU grace period.
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*/
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static void amdgpu_job_fence_free(struct rcu_head *rcu)
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{
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struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
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/* free job if fence has a parent job */
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kfree(container_of(f, struct amdgpu_job, hw_fence));
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}
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/**
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@ -720,6 +749,19 @@ static void amdgpu_fence_release(struct dma_fence *f)
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call_rcu(&f->rcu, amdgpu_fence_free);
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}
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/**
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* amdgpu_job_fence_release - callback that job embedded fence can be freed
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*
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* @f: fence
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*
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* This is the simliar function with amdgpu_fence_release above, it
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* only handles the job embedded fence.
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*/
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static void amdgpu_job_fence_release(struct dma_fence *f)
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{
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call_rcu(&f->rcu, amdgpu_job_fence_free);
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}
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static const struct dma_fence_ops amdgpu_fence_ops = {
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.get_driver_name = amdgpu_fence_get_driver_name,
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.get_timeline_name = amdgpu_fence_get_timeline_name,
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@ -727,6 +769,12 @@ static const struct dma_fence_ops amdgpu_fence_ops = {
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.release = amdgpu_fence_release,
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};
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static const struct dma_fence_ops amdgpu_job_fence_ops = {
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.get_driver_name = amdgpu_fence_get_driver_name,
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.get_timeline_name = amdgpu_job_fence_get_timeline_name,
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.enable_signaling = amdgpu_job_fence_enable_signaling,
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.release = amdgpu_job_fence_release,
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};
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/*
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* Fence debugfs
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@ -53,9 +53,6 @@ enum amdgpu_ring_priority_level {
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#define AMDGPU_FENCE_FLAG_INT (1 << 1)
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#define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2)
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/* fence flag bit to indicate the face is embedded in job*/
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#define AMDGPU_FENCE_FLAG_EMBED_IN_JOB_BIT (DMA_FENCE_FLAG_USER_BITS + 1)
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#define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched)
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#define AMDGPU_IB_POOL_SIZE (1024 * 1024)
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@ -114,6 +111,7 @@ struct amdgpu_fence_driver {
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struct dma_fence **fences;
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};
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void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring);
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void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
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int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
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