drm/amdgpu: add cache flush workaround to gfx8 emit_fence
The same workaround is used for gfx7. Both PAL and Mesa use it for gfx8 too, so port this commit to gfx_v8_0_ring_emit_fence_gfx. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -6146,7 +6146,23 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
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bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
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bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
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/* EVENT_WRITE_EOP - flush caches, send int */
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/* Workaround for cache flush problems. First send a dummy EOP
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* event down the pipe with seq one below.
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*/
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amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
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amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
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EOP_TC_ACTION_EN |
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EOP_TC_WB_ACTION_EN |
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EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
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EVENT_INDEX(5)));
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amdgpu_ring_write(ring, addr & 0xfffffffc);
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amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
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DATA_SEL(1) | INT_SEL(0));
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amdgpu_ring_write(ring, lower_32_bits(seq - 1));
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amdgpu_ring_write(ring, upper_32_bits(seq - 1));
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/* Then send the real EOP event down the pipe:
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* EVENT_WRITE_EOP - flush caches, send int */
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amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
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amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN |
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EOP_TC_ACTION_EN |
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@ -6888,7 +6904,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
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5 + /* COND_EXEC */
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7 + /* PIPELINE_SYNC */
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VI_FLUSH_GPU_TLB_NUM_WREG * 5 + 9 + /* VM_FLUSH */
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8 + /* FENCE for VM_FLUSH */
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12 + /* FENCE for VM_FLUSH */
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20 + /* GDS switch */
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4 + /* double SWITCH_BUFFER,
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the first COND_EXEC jump to the place just
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@ -6900,7 +6916,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = {
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31 + /* DE_META */
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3 + /* CNTX_CTRL */
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5 + /* HDP_INVL */
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8 + 8 + /* FENCE x2 */
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12 + 12 + /* FENCE x2 */
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2, /* SWITCH_BUFFER */
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.emit_ib_size = 4, /* gfx_v8_0_ring_emit_ib_gfx */
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.emit_ib = gfx_v8_0_ring_emit_ib_gfx,
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