drm/amd/display: fix B0 TMDS deepcolor no dislay issue
[why] B0 PHY C map to F, D map to G driver use logic instance, dmub does the remap. Driver still need use the right PHY instance to access right HW. [how] use phyical instance when program PHY register. [note] could move resync_control programming to dmub next. Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
b6fd6e0f5e
commit
bf252ce1fa
|
@ -355,6 +355,14 @@ static const struct dce110_clk_src_regs clk_src_regs[] = {
|
||||||
clk_src_regs(3, D),
|
clk_src_regs(3, D),
|
||||||
clk_src_regs(4, E)
|
clk_src_regs(4, E)
|
||||||
};
|
};
|
||||||
|
/*pll_id being rempped in dmub, in driver it is logical instance*/
|
||||||
|
static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
|
||||||
|
clk_src_regs(0, A),
|
||||||
|
clk_src_regs(1, B),
|
||||||
|
clk_src_regs(2, F),
|
||||||
|
clk_src_regs(3, G),
|
||||||
|
clk_src_regs(4, E)
|
||||||
|
};
|
||||||
|
|
||||||
static const struct dce110_clk_src_shift cs_shift = {
|
static const struct dce110_clk_src_shift cs_shift = {
|
||||||
CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
|
CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
|
||||||
|
@ -2294,14 +2302,27 @@ static bool dcn31_resource_construct(
|
||||||
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
||||||
CLOCK_SOURCE_COMBO_PHY_PLL1,
|
CLOCK_SOURCE_COMBO_PHY_PLL1,
|
||||||
&clk_src_regs[1], false);
|
&clk_src_regs[1], false);
|
||||||
pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
|
/*move phypllx_pixclk_resync to dmub next*/
|
||||||
|
if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
|
||||||
|
pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
|
||||||
|
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
||||||
|
CLOCK_SOURCE_COMBO_PHY_PLL2,
|
||||||
|
&clk_src_regs_b0[2], false);
|
||||||
|
pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
|
||||||
|
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
||||||
|
CLOCK_SOURCE_COMBO_PHY_PLL3,
|
||||||
|
&clk_src_regs_b0[3], false);
|
||||||
|
} else {
|
||||||
|
pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
|
||||||
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
||||||
CLOCK_SOURCE_COMBO_PHY_PLL2,
|
CLOCK_SOURCE_COMBO_PHY_PLL2,
|
||||||
&clk_src_regs[2], false);
|
&clk_src_regs[2], false);
|
||||||
pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
|
pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
|
||||||
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
||||||
CLOCK_SOURCE_COMBO_PHY_PLL3,
|
CLOCK_SOURCE_COMBO_PHY_PLL3,
|
||||||
&clk_src_regs[3], false);
|
&clk_src_regs[3], false);
|
||||||
|
}
|
||||||
|
|
||||||
pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
|
pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
|
||||||
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
dcn30_clock_source_create(ctx, ctx->dc_bios,
|
||||||
CLOCK_SOURCE_COMBO_PHY_PLL4,
|
CLOCK_SOURCE_COMBO_PHY_PLL4,
|
||||||
|
|
|
@ -49,4 +49,35 @@ struct resource_pool *dcn31_create_resource_pool(
|
||||||
const struct dc_init_data *init_data,
|
const struct dc_init_data *init_data,
|
||||||
struct dc *dc);
|
struct dc *dc);
|
||||||
|
|
||||||
|
/*temp: B0 specific before switch to dcn313 headers*/
|
||||||
|
#ifndef regPHYPLLF_PIXCLK_RESYNC_CNTL
|
||||||
|
#define regPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e
|
||||||
|
#define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
||||||
|
#define regPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f
|
||||||
|
#define regPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1
|
||||||
|
|
||||||
|
//PHYPLLF_PIXCLK_RESYNC_CNTL
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE__SHIFT 0x8
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_ENABLE_MASK 0x00000100L
|
||||||
|
#define PHYPLLF_PIXCLK_RESYNC_CNTL__PHYPLLF_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
|
||||||
|
|
||||||
|
//PHYPLLG_PIXCLK_RESYNC_CNTL
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE__SHIFT 0x0
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS__SHIFT 0x1
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL__SHIFT 0x4
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE__SHIFT 0x8
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE__SHIFT 0x9
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_RESYNC_ENABLE_MASK 0x00000001L
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DEEP_COLOR_DTO_ENABLE_STATUS_MASK 0x00000002L
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_DCCG_DEEP_COLOR_CNTL_MASK 0x00000030L
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_ENABLE_MASK 0x00000100L
|
||||||
|
#define PHYPLLG_PIXCLK_RESYNC_CNTL__PHYPLLG_PIXCLK_DOUBLE_RATE_ENABLE_MASK 0x00000200L
|
||||||
|
#endif
|
||||||
#endif /* _DCN31_RESOURCE_H_ */
|
#endif /* _DCN31_RESOURCE_H_ */
|
||||||
|
|
Loading…
Reference in New Issue