drm/i915/perf: fix whitelist on Gen10+
Gen10 added an additional NOA_WRITE register (high bits) and we forgot
to whitelist it for userspace.
Fixes: 95690a02fb
("drm/i915/perf: enable perf support on CNL")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190601225845.12600-1-lionel.g.landwerlin@intel.com
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@ -3027,6 +3027,7 @@ static bool gen8_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
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static bool gen10_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr)
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{
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return gen8_is_valid_mux_addr(dev_priv, addr) ||
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addr == i915_mmio_reg_offset(GEN10_NOA_WRITE_HIGH) ||
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(addr >= i915_mmio_reg_offset(OA_PERFCNT3_LO) &&
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addr <= i915_mmio_reg_offset(OA_PERFCNT4_HI));
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}
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@ -1063,6 +1063,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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#define NOA_DATA _MMIO(0x986C)
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#define NOA_WRITE _MMIO(0x9888)
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#define GEN10_NOA_WRITE_HIGH _MMIO(0x9884)
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#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
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#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
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