arm64: dts: ti: k3-j721e: Update the power domain cells
Update the power-domain cells to 2 and mark all devices as exclusive. Main uart 0 is the debug console for processor boards and it is used by different software entities like u-boot, atf, linux simultaneously. So just mark main_uart0 as shared device for common processor board. Reviewed-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
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@ -19,6 +19,10 @@
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status = "disabled";
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};
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&main_uart0 {
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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};
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&main_uart3 {
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/* UART not brought out */
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status = "disabled";
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@ -119,7 +119,7 @@
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 146>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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};
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@ -132,7 +132,7 @@
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 278>;
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power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 278 0>;
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clock-names = "fclk";
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};
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@ -145,7 +145,7 @@
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 279>;
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power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 279 0>;
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clock-names = "fclk";
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};
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@ -158,7 +158,7 @@
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 280>;
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power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 280 0>;
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clock-names = "fclk";
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};
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@ -171,7 +171,7 @@
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 281>;
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power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 281 0>;
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clock-names = "fclk";
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};
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@ -184,7 +184,7 @@
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 282>;
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power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 282 0>;
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clock-names = "fclk";
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};
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@ -197,7 +197,7 @@
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 283>;
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power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 283 0>;
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clock-names = "fclk";
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};
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@ -210,7 +210,7 @@
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 284>;
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power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 284 0>;
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clock-names = "fclk";
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};
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@ -223,7 +223,7 @@
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interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 285>;
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power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 285 0>;
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clock-names = "fclk";
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};
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@ -236,7 +236,7 @@
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interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 286>;
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power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 286 0>;
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clock-names = "fclk";
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};
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@ -20,7 +20,7 @@
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <1>;
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#power-domain-cells = <2>;
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};
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k3_clks: clocks {
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@ -59,7 +59,7 @@
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 287>;
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power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 287 0>;
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clock-names = "fclk";
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};
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@ -72,7 +72,7 @@
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <96000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 149>;
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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};
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@ -8,6 +8,7 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/k3.h>
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#include <dt-bindings/soc/ti,sci_pm_domain.h>
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/ {
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model = "Texas Instruments K3 J721E SoC";
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