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ARM: dts: rockchip: add operating points and armclk references 

Add basic OPP entries for current supported Rockchip SoCs.
The operating points are currently very conservative, so individual
boards may opt to redefine them.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Heiko Stuebner 2014-09-13 00:34:29 +02:00
parent f114040e3e
commit be8a77c548
3 changed files with 43 additions and 3 deletions
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12
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -26,11 +26,21 @@
#size-cells = <0>;
enable-method = "rockchip,rk3066-smp";
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
operating-points = <
/* kHz uV */
1008000 1075000
816000 1025000
600000 1025000
504000 1000000
312000 975000
>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu@1 {
device_type = "cpu";

15
arch/arm/boot/dts/rk3188.dtsi
View File

@ -26,11 +26,24 @@
#size-cells = <0>;
enable-method = "rockchip,rk3066-smp";
cpu@0 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x0>;
operating-points = <
/* kHz uV */
1608000 1350000
1416000 1250000
1200000 1150000
1008000 1075000
816000 975000
600000 950000
504000 925000
312000 875000
>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu@1 {
device_type = "cpu";

19
arch/arm/boot/dts/rk3288.dtsi
View File

@ -47,10 +47,27 @@
#address-cells = <1>;
#size-cells = <0>;
cpu@500 {
cpu0: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x500>;
operating-points = <
/* KHz uV */
1608000 1350000
1512000 1300000
1416000 1200000
1200000 1100000
1008000 1050000
816000 1000000
696000 950000
600000 900000
408000 900000
312000 900000
216000 900000
126000 900000
>;
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
cpu@501 {
device_type = "cpu";