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perf vendor events s390: Add cache metrics for z15 

Add metrics for s390 z15

- Percentage sourced from Level 2 cache
- Percentage sourced from Level 3 on same chip cache
- Percentage sourced from Level 4 Local cache on same book
- Percentage sourced from Level 4 Remote cache on different book
- Percentage sourced from memory

For details about the formulas see this documentation:

  https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf

Outpuf after:
  # ./perf stat -M l4rp -- find /
  .... find output deleted

  Performance counter stats for 'find /':

              5      L1I_OFFDRAWER_L4_SOURCED_WRITES  #     0.01 l4rp
            187      L1D_OFFDRAWER_L4_SOURCED_WRITES
              0      L1I_OFFDRAWER_L3_SOURCED_WRITES
    231,333,165      L1I_DIR_WRITES
          3,303      L1D_OFFDRAWER_L3_SOURCED_WRITES
         47,461      L1D_OFFDRAWER_L3_SOURCED_WRITES_IV
              0      L1I_OFFDRAWER_L3_SOURCED_WRITES_IV
    126,706,244      L1D_DIR_WRITES

   27.870355461 seconds time elapsed

    0.521562000 seconds user
   12.494503000 seconds sys
  #

Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-By: Sumanth Korikkar <sumanthk@linux.ibm.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Heiko Carstens <hca@linux.ibm.com>
Cc: Sven Schnelle <svens@linux.ibm.com>
Cc: Vasily Gorbik <gor@linux.ibm.com>
Link: https://lore.kernel.org/r/20230313080201.2440201-3-tmricht@linux.ibm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Thomas Richter 2023-03-13 09:01:58 +01:00 committed by Arnaldo Carvalho de Melo
parent 3da9559e41
commit bdecfecac8
1 changed files with 25 additions and 0 deletions
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25
tools/perf/pmu-events/arch/s390/cf_z15/transaction.json
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@ -18,5 +18,30 @@
"BriefDescription": "Level One Miss per 100 Instructions",
"MetricName": "l1mp",
"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
},
{
"BriefDescription": "Percentage sourced from Level 2 cache",
"MetricName": "l2p",
"MetricExpr": "((L1D_L2D_SOURCED_WRITES + L1I_L2I_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
},
{
"BriefDescription": "Percentage sourced from Level 3 on same chip cache",
"MetricName": "l3p",
"MetricExpr": "((L1D_ONCHIP_L3_SOURCED_WRITES + L1D_ONCHIP_L3_SOURCED_WRITES_IV + L1I_ONCHIP_L3_SOURCED_WRITES + L1I_ONCHIP_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
},
{
"BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
"MetricName": "l4lp",
"MetricExpr": "((L1D_ONCLUSTER_L3_SOURCED_WRITES + L1D_ONCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONDRAWER_L4_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES + L1I_ONCLUSTER_L3_SOURCED_WRITES_IV + L1I_ONDRAWER_L4_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES + L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV + L1D_ONCHIP_L3_SOURCED_WRITES_RO + L1I_OFFCLUSTER_L3_SOURCED_WRITES + L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
},
{
"BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
"MetricName": "l4rp",
"MetricExpr": "((L1D_OFFDRAWER_L3_SOURCED_WRITES + L1D_OFFDRAWER_L3_SOURCED_WRITES_IV + L1D_OFFDRAWER_L4_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES + L1I_OFFDRAWER_L3_SOURCED_WRITES_IV + L1I_OFFDRAWER_L4_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
},
{
"BriefDescription": "Percentage sourced from memory",
"MetricName": "memp",
"MetricExpr": "((L1D_ONCHIP_MEMORY_SOURCED_WRITES + L1D_ONCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1D_OFFDRAWER_MEMORY_SOURCED_WRITES + L1I_ONCHIP_MEMORY_SOURCED_WRITES + L1I_ONCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES + L1I_OFFDRAWER_MEMORY_SOURCED_WRITES) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
}
]