iommu/amd: Fix typos for PPR macros
The bit 13 and bit 14 of the IOMMU control register are PPRLogEn and PPRIntEn. They are related to PPR (Peripheral Page Request) instead of 'PPF'. Fix them accrodingly. Signed-off-by: Adrian Huang <ahuang12@lenovo.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
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@ -716,7 +716,7 @@ static void iommu_enable_ppr_log(struct amd_iommu *iommu)
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writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
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writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
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iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
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iommu_feature_enable(iommu, CONTROL_PPRLOG_EN);
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iommu_feature_enable(iommu, CONTROL_PPR_EN);
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}
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@ -2031,7 +2031,7 @@ enable_faults:
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iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
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if (iommu->ppr_log != NULL)
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iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
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iommu_feature_enable(iommu, CONTROL_PPRINT_EN);
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iommu_ga_log_enable(iommu);
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@ -147,8 +147,8 @@
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#define CONTROL_COHERENT_EN 0x0aULL
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#define CONTROL_ISOC_EN 0x0bULL
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#define CONTROL_CMDBUF_EN 0x0cULL
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#define CONTROL_PPFLOG_EN 0x0dULL
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#define CONTROL_PPFINT_EN 0x0eULL
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#define CONTROL_PPRLOG_EN 0x0dULL
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#define CONTROL_PPRINT_EN 0x0eULL
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#define CONTROL_PPR_EN 0x0fULL
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#define CONTROL_GT_EN 0x10ULL
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#define CONTROL_GA_EN 0x11ULL
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