drm/i915/adl_p: ADL_P device info enabling
Add ADL-P to the device_info table and support MACROS. Bspec: 49185, 55372, 55373 Cc: Matt Atwood <matthew.s.atwood@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210506161930.309688-4-imre.deak@intel.com
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@ -552,6 +552,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = {
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INTEL_TGL_12_IDS(&gen11_early_ops),
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INTEL_TGL_12_IDS(&gen11_early_ops),
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INTEL_RKL_IDS(&gen11_early_ops),
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INTEL_RKL_IDS(&gen11_early_ops),
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INTEL_ADLS_IDS(&gen11_early_ops),
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INTEL_ADLS_IDS(&gen11_early_ops),
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INTEL_ADLP_IDS(&gen11_early_ops),
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};
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};
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struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
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struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
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@ -1392,6 +1392,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
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#define IS_ROCKETLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ROCKETLAKE)
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#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
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#define IS_DG1(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG1)
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#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
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#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
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#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
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#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
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#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
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#define IS_BDW_ULT(dev_priv) \
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#define IS_BDW_ULT(dev_priv) \
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@ -949,6 +949,17 @@ static const struct intel_device_info adl_s_info = {
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.dbuf.size = 4096, \
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.dbuf.size = 4096, \
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.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
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.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | BIT(DBUF_S4)
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static const struct intel_device_info adl_p_info = {
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GEN12_FEATURES,
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XE_LPD_FEATURES,
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PLATFORM(INTEL_ALDERLAKE_P),
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.require_force_probe = 1,
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.platform_engine_mask =
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BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
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.ppgtt_size = 48,
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.dma_mask_size = 39,
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};
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#undef GEN
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#undef GEN
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#undef PLATFORM
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#undef PLATFORM
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@ -1026,6 +1037,7 @@ static const struct pci_device_id pciidlist[] = {
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INTEL_TGL_12_IDS(&tgl_info),
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INTEL_TGL_12_IDS(&tgl_info),
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INTEL_RKL_IDS(&rkl_info),
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INTEL_RKL_IDS(&rkl_info),
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INTEL_ADLS_IDS(&adl_s_info),
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INTEL_ADLS_IDS(&adl_s_info),
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INTEL_ADLP_IDS(&adl_p_info),
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{0, 0, 0}
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{0, 0, 0}
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};
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};
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MODULE_DEVICE_TABLE(pci, pciidlist);
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MODULE_DEVICE_TABLE(pci, pciidlist);
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@ -67,6 +67,7 @@ static const char * const platform_names[] = {
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PLATFORM_NAME(ROCKETLAKE),
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PLATFORM_NAME(ROCKETLAKE),
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PLATFORM_NAME(DG1),
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PLATFORM_NAME(DG1),
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PLATFORM_NAME(ALDERLAKE_S),
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PLATFORM_NAME(ALDERLAKE_S),
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PLATFORM_NAME(ALDERLAKE_P),
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};
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};
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#undef PLATFORM_NAME
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#undef PLATFORM_NAME
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@ -87,6 +87,7 @@ enum intel_platform {
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INTEL_ROCKETLAKE,
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INTEL_ROCKETLAKE,
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INTEL_DG1,
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INTEL_DG1,
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INTEL_ALDERLAKE_S,
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INTEL_ALDERLAKE_S,
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INTEL_ALDERLAKE_P,
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INTEL_MAX_PLATFORMS
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INTEL_MAX_PLATFORMS
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};
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};
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