ARM64: dts: meson-gxm: add SCPI configuration for GXM
This adds the SCPI DVFS clock index and configures the CPU cores accordingly. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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@ -85,6 +85,7 @@
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reg = <0x0 0x100>;
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reg = <0x0 0x100>;
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enable-method = "psci";
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enable-method = "psci";
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next-level-cache = <&l2>;
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next-level-cache = <&l2>;
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clocks = <&scpi_dvfs 1>;
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};
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};
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cpu5: cpu@101 {
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cpu5: cpu@101 {
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@ -93,6 +94,7 @@
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reg = <0x0 0x101>;
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reg = <0x0 0x101>;
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enable-method = "psci";
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enable-method = "psci";
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next-level-cache = <&l2>;
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next-level-cache = <&l2>;
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clocks = <&scpi_dvfs 1>;
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};
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};
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cpu6: cpu@102 {
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cpu6: cpu@102 {
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@ -101,6 +103,7 @@
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reg = <0x0 0x102>;
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reg = <0x0 0x102>;
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enable-method = "psci";
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enable-method = "psci";
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next-level-cache = <&l2>;
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next-level-cache = <&l2>;
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clocks = <&scpi_dvfs 1>;
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};
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};
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cpu7: cpu@103 {
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cpu7: cpu@103 {
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@ -109,10 +112,17 @@
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reg = <0x0 0x103>;
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reg = <0x0 0x103>;
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enable-method = "psci";
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enable-method = "psci";
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next-level-cache = <&l2>;
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next-level-cache = <&l2>;
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clocks = <&scpi_dvfs 1>;
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};
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};
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};
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};
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};
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};
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&scpi_dvfs {
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clock-indices = <0 1>;
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clock-output-names = "vbig", "vlittle";
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};
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&vpu {
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&vpu {
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compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
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compatible = "amlogic,meson-gxm-vpu", "amlogic,meson-gx-vpu";
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};
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};
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