ARM i.MX5: Add System Reset Controller (SRC) support for i.MX51 and i.MX53
The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus the IPU2 reset line and multi core CPU reset/enable bits. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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@ -520,7 +520,7 @@
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};
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src: src@020d8000 {
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compatible = "fsl,imx6q-src";
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compatible = "fsl,imx6q-src", "fsl,imx51-src";
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reg = <0x020d8000 0x4000>;
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interrupts = <0 91 0x04 0 96 0x04>;
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#reset-cells = <1>;
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@ -149,6 +149,7 @@ config SOC_IMX5
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config SOC_IMX51
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bool
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select HAVE_IMX_SRC
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select PINCTRL
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select PINCTRL_IMX51
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select SOC_IMX5
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@ -774,6 +775,7 @@ comment "Device tree only"
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config SOC_IMX53
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bool "i.MX53 support"
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select HAVE_CAN_FLEXCAN if CAN
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select HAVE_IMX_SRC
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select IMX_HAVE_PLATFORM_IMX2_WDT
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select PINCTRL
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select PINCTRL_IMX53
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@ -84,6 +84,7 @@ void __init imx51_init_early(void)
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mxc_set_cpu_type(MXC_CPU_MX51);
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mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
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imx_src_init();
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}
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void __init imx53_init_early(void)
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@ -91,6 +92,7 @@ void __init imx53_init_early(void)
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mxc_set_cpu_type(MXC_CPU_MX53);
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mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
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mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
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imx_src_init();
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}
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void __init mx51_init_irq(void)
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@ -61,7 +61,9 @@ void __init imx_src_init(void)
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struct device_node *np;
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u32 val;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-src");
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np = of_find_compatible_node(NULL, NULL, "fsl,imx51-src");
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if (!np)
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return;
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src_base = of_iomap(np, 0);
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WARN_ON(!src_base);
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