ALSA: firewire-lib: code refactoring to start several IT/IR contexts
It's several hundred cycles from starting isochronous contexts and the actual cycle to start processing content of packet. It's useless to start the context for IRQ target apart from the other contexts. This commit refactors helper function to start AMDTP domain in the point. Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp> Link: https://lore.kernel.org/r/20210520040154.80450-7-o-takashi@sakamocchi.jp Signed-off-by: Takashi Iwai <tiwai@suse.de>
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@ -1223,8 +1223,6 @@ static void amdtp_stream_first_callback(struct fw_iso_context *context,
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* @s: the AMDTP stream to start
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* @channel: the isochronous channel on the bus
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* @speed: firewire speed code
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* @start_cycle: the isochronous cycle to start the context. Start immediately
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* if negative value is given.
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* @queue_size: The number of packets in the queue.
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* @idle_irq_interval: the interval to queue packet during initial state.
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*
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@ -1233,8 +1231,7 @@ static void amdtp_stream_first_callback(struct fw_iso_context *context,
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* device can be started.
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*/
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static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
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int start_cycle, unsigned int queue_size,
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unsigned int idle_irq_interval)
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unsigned int queue_size, unsigned int idle_irq_interval)
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{
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bool is_irq_target = (s == s->domain->irq_target);
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unsigned int ctx_header_size;
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@ -1298,6 +1295,9 @@ static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
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if (s->direction == AMDTP_IN_STREAM) {
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s->ctx_data.tx.max_ctx_payload_length = max_ctx_payload_size;
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s->ctx_data.tx.ctx_header_size = ctx_header_size;
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} else {
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s->ctx_data.rx.seq_index = 0;
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s->ctx_data.rx.event_count = 0;
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}
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if (s->flags & CIP_NO_HEADER)
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@ -1341,7 +1341,7 @@ static int amdtp_stream_start(struct amdtp_stream *s, int channel, int speed,
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tag |= FW_ISO_CONTEXT_MATCH_TAG0;
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s->callbacked = false;
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err = fw_iso_context_start(s->context, start_cycle, 0, tag);
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err = fw_iso_context_start(s->context, -1, 0, tag);
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if (err < 0)
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goto err_pkt_descs;
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@ -1559,7 +1559,6 @@ int amdtp_domain_start(struct amdtp_domain *d, unsigned int tx_init_skip_cycles)
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};
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unsigned int events_per_buffer = d->events_per_buffer;
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unsigned int events_per_period = d->events_per_period;
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unsigned int idle_irq_interval;
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unsigned int queue_size;
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struct amdtp_stream *s;
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int err;
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@ -1598,27 +1597,19 @@ int amdtp_domain_start(struct amdtp_domain *d, unsigned int tx_init_skip_cycles)
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d->last_syt_offset = TICKS_PER_CYCLE;
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list_for_each_entry(s, &d->streams, list) {
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if (s->direction == AMDTP_OUT_STREAM)
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s->ctx_data.rx.seq_index = 0;
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unsigned int idle_irq_interval = 0;
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if (s != d->irq_target) {
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err = amdtp_stream_start(s, s->channel, s->speed, -1, queue_size, 0);
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if (err < 0)
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goto error;
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if (s->direction == AMDTP_OUT_STREAM && s == d->irq_target) {
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idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period,
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amdtp_rate_table[d->irq_target->sfc]);
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}
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// Starts immediately but actually DMA context starts several hundred cycles later.
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err = amdtp_stream_start(s, s->channel, s->speed, queue_size, idle_irq_interval);
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if (err < 0)
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goto error;
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}
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s = d->irq_target;
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s->ctx_data.rx.event_count = 0;
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s->ctx_data.rx.seq_index = 0;
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idle_irq_interval = DIV_ROUND_UP(CYCLES_PER_SECOND * events_per_period,
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amdtp_rate_table[d->irq_target->sfc]);
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err = amdtp_stream_start(s, s->channel, s->speed, -1, queue_size,
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idle_irq_interval);
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if (err < 0)
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goto error;
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return 0;
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error:
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list_for_each_entry(s, &d->streams, list)
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