bpf: Fix mask generation for 32-bit narrow loads of 64-bit fields
commit0613d8ca9a
upstream. A narrow load from a 64-bit context field results in a 64-bit load followed potentially by a 64-bit right-shift and then a bitwise AND operation to extract the relevant data. In the case of a 32-bit access, an immediate mask of 0xffffffff is used to construct a 64-bit BPP_AND operation which then sign-extends the mask value and effectively acts as a glorified no-op. For example: 0: 61 10 00 00 00 00 00 00 r0 = *(u32 *)(r1 + 0) results in the following code generation for a 64-bit field: ldr x7, [x7] // 64-bit load mov x10, #0xffffffffffffffff and x7, x7, x10 Fix the mask generation so that narrow loads always perform a 32-bit AND operation: ldr x7, [x7] // 64-bit load mov w10, #0xffffffff and w7, w7, w10 Cc: Alexei Starovoitov <ast@kernel.org> Cc: Daniel Borkmann <daniel@iogearbox.net> Cc: John Fastabend <john.fastabend@gmail.com> Cc: Krzesimir Nowak <krzesimir@kinvolk.io> Cc: Andrey Ignatov <rdna@fb.com> Acked-by: Yonghong Song <yhs@fb.com> Fixes:31fd85816d
("bpf: permits narrower load from bpf program context fields") Signed-off-by: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20230518102528.1341-1-will@kernel.org Signed-off-by: Alexei Starovoitov <ast@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Jianping Liu <frankjpliu@tencent.com>
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@ -10161,7 +10161,7 @@ static int convert_ctx_accesses(struct bpf_verifier_env *env)
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insn_buf[cnt++] = BPF_ALU64_IMM(BPF_RSH,
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insn->dst_reg,
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shift);
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insn_buf[cnt++] = BPF_ALU64_IMM(BPF_AND, insn->dst_reg,
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insn_buf[cnt++] = BPF_ALU32_IMM(BPF_AND, insn->dst_reg,
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(1ULL << size * 8) - 1);
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}
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}
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