From bd08a8d9e8dd6b77a990372fc1233765ca9175e9 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 19 Mar 2018 17:28:28 +0800 Subject: [PATCH] drm/amdgpu/nbio6: Correct PCIE_INDEX/DATA pair used for smn register accessing PCIE_INDEX2/DATA2 pair will be used for smn register accessing since from vega. PCIE_INDEX/DATA pair should be reserved for smu Signed-off-by: Hawking Zhang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 1cf34248dff4..6f9c54978cc1 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -220,12 +220,12 @@ static u32 nbio_v6_1_get_hdp_flush_done_offset(struct amdgpu_device *adev) static u32 nbio_v6_1_get_pcie_index_offset(struct amdgpu_device *adev) { - return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX); + return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2); } static u32 nbio_v6_1_get_pcie_data_offset(struct amdgpu_device *adev) { - return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA); + return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2); } static const struct nbio_hdp_flush_reg nbio_v6_1_hdp_flush_reg = {