ARM: cpu hotplug: remove majority of cache flushing from platforms
Remove the majority of cache flushing calls from the individual platform files. This is now handled by the core code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -28,7 +28,6 @@ static inline void cpu_enter_lowpower_a9(void)
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{
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unsigned int v;
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flush_cache_all();
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asm volatile(
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" mcr p15, 0, %1, c7, c5, 0\n"
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" mcr p15, 0, %1, c7, c10, 4\n"
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@ -15,8 +15,6 @@
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*/
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#include <linux/kernel.h>
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#include <asm/cacheflush.h>
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#include "core.h"
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#include "sysregs.h"
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@ -28,8 +26,6 @@ extern void secondary_startup(void);
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*/
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void __ref highbank_cpu_die(unsigned int cpu)
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{
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flush_cache_all();
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highbank_set_cpu_jump(cpu, phys_to_virt(0));
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highbank_set_core_pwr();
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@ -11,7 +11,6 @@
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*/
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#include <linux/errno.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include "common.h"
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@ -20,7 +19,6 @@ static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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flush_cache_all();
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asm volatile(
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"mcr p15, 0, %1, c7, c5, 0\n"
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" mcr p15, 0, %1, c7, c10, 4\n"
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@ -10,16 +10,12 @@
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include "common.h"
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static inline void cpu_enter_lowpower(void)
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{
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/* Just flush the cache. Changing the coherency is not yet
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* available on msm. */
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flush_cache_all();
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}
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static inline void cpu_leave_lowpower(void)
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@ -35,9 +35,6 @@ void __ref omap4_cpu_die(unsigned int cpu)
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unsigned int boot_cpu = 0;
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void __iomem *base = omap_get_wakeupgen_base();
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flush_cache_all();
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dsb();
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/*
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* we're ready for shutdown now, so do it
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*/
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@ -10,13 +10,10 @@
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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static inline void platform_do_lowpower(unsigned int cpu)
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{
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flush_cache_all();
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/* we put the platform to just WFI */
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for (;;) {
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__asm__ __volatile__("dsb\n\t" "wfi\n\t"
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@ -12,7 +12,6 @@
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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@ -20,7 +19,6 @@ static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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flush_cache_all();
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asm volatile(
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" mcr p15, 0, %1, c7, c5, 0\n"
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" mcr p15, 0, %1, c7, c10, 4\n"
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@ -119,14 +119,6 @@ static int sh73a0_cpu_kill(unsigned int cpu)
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static void sh73a0_cpu_die(unsigned int cpu)
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{
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/*
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* The ARM MPcore does not issue a cache coherency request for the L1
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* cache when powering off single CPUs. We must take care of this and
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* further caches.
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*/
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dsb();
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flush_cache_all();
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/* Set power off mode. This takes the CPU out of the MP cluster */
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scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
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@ -13,7 +13,6 @@
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/cp15.h>
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#include <asm/smp_plat.h>
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@ -21,7 +20,6 @@ static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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flush_cache_all();
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asm volatile(
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" mcr p15, 0, %1, c7, c5, 0\n"
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" dsb\n"
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@ -12,7 +12,6 @@
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#include <linux/smp.h>
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#include <linux/clk/tegra.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include "sleep.h"
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@ -12,7 +12,6 @@
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <mach/setup.h>
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@ -24,8 +23,6 @@
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*/
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void __ref ux500_cpu_die(unsigned int cpu)
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{
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flush_cache_all();
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/* directly enter low power state, skipping secure registers */
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for (;;) {
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__asm__ __volatile__("dsb\n\t" "wfi\n\t"
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@ -12,7 +12,6 @@
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#include <linux/errno.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/cp15.h>
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@ -20,7 +19,6 @@ static inline void cpu_enter_lowpower(void)
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{
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unsigned int v;
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flush_cache_all();
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asm volatile(
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"mcr p15, 0, %1, c7, c5, 0\n"
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" mcr p15, 0, %1, c7, c10, 4\n"
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