PCI: imx6: Fix bugs in PCIe startup code
LTSSM shouldn't be set once in assert_core_reset(). Move peripheral reset just before LTSSM start. Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Cc: Frank Li <lznuaa@gmail.com> Cc: Harro Haan <hrhaan@gmail.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Mohit KUMAR <Mohit.KUMAR@st.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Richard Zhu <r65037@freescale.com> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Sean Cross <xobs@kosagi.com> Cc: Siva Reddy Kallam <siva.kallam@samsung.com> Cc: Srikanth T Shivanand <ts.srikanth@samsung.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Yinghai Lu <yinghai@kernel.org>
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@ -220,18 +220,9 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
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IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
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IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
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/* Some boards don't have PCIe reset GPIO. */
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if (gpio_is_valid(imx6_pcie->reset_gpio)) {
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gpio_set_value(imx6_pcie->reset_gpio, 0);
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msleep(100);
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gpio_set_value(imx6_pcie->reset_gpio, 1);
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}
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return 0;
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return 0;
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}
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}
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@ -275,6 +266,12 @@ static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
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/* allow the clocks to stabilize */
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/* allow the clocks to stabilize */
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usleep_range(200, 500);
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usleep_range(200, 500);
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/* Some boards don't have PCIe reset GPIO. */
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if (gpio_is_valid(imx6_pcie->reset_gpio)) {
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gpio_set_value(imx6_pcie->reset_gpio, 0);
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msleep(100);
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gpio_set_value(imx6_pcie->reset_gpio, 1);
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}
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return 0;
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return 0;
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err_pcie_axi:
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err_pcie_axi:
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