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OpenCloudOS-Kernel
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Merge branch 'omap-for-v5.5/pm' into omap-for-v5.5/soc

This commit is contained in:
Tony Lindgren 2019-10-23 10:42:39 -07:00
parent 1994ebd1f7 0a4818c192
commit bc794744cd
28 changed files with 419 additions and 184 deletions
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2
arch/arm/boot/dts/am335x-icev2.dts
View File

@ -432,7 +432,7 @@
pinctrl-0 = <&mmc0_pins_default>; pinctrl-0 = <&mmc0_pins_default>;
}; };
&gpio0 { &gpio0_target {
/* Do not idle the GPIO used for holding the VTT regulator */ /* Do not idle the GPIO used for holding the VTT regulator */
ti,no-reset-on-init; ti,no-reset-on-init;
ti,no-idle-on-init; ti,no-idle-on-init;

6
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -127,7 +127,7 @@
ranges = <0x0 0x5000 0x1000>; ranges = <0x0 0x5000 0x1000>;
}; };
target-module@7000 { /* 0x44e07000, ap 14 20.0 */ gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio1"; ti,hwmods = "gpio1";
reg = <0x7000 0x4>, reg = <0x7000 0x4>,
@ -2038,7 +2038,9 @@
reg = <0xe000 0x4>, reg = <0xe000 0x4>,
<0xe054 0x4>; <0xe054 0x4>;
reg-names = "rev", "sysc"; reg-names = "rev", "sysc";
ti,sysc-midle ; ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>, ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>, <SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;

9
arch/arm/boot/dts/am3874-iceboard.dts
View File

@ -111,13 +111,13 @@
reg = <0x70>; reg = <0x70>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
i2c-mux-idle-disconnect;
i2c@0 { i2c@0 {
/* FMC A */ /* FMC A */
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0>; reg = <0>;
i2c-mux-idle-disconnect;
}; };
i2c@1 { i2c@1 {
@ -125,7 +125,6 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <1>; reg = <1>;
i2c-mux-idle-disconnect;
}; };
i2c@2 { i2c@2 {
@ -133,7 +132,6 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <2>; reg = <2>;
i2c-mux-idle-disconnect;
}; };
i2c@3 { i2c@3 {
@ -141,7 +139,6 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <3>; reg = <3>;
i2c-mux-idle-disconnect;
}; };
i2c@4 { i2c@4 {
@ -149,14 +146,12 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <4>; reg = <4>;
i2c-mux-idle-disconnect;
}; };
i2c@5 { i2c@5 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <5>; reg = <5>;
i2c-mux-idle-disconnect;
ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; }; ina230@40 { compatible = "ti,ina230"; reg = <0x40>; shunt-resistor = <5000>; };
ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; }; ina230@41 { compatible = "ti,ina230"; reg = <0x41>; shunt-resistor = <5000>; };
@ -182,14 +177,12 @@
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <6>; reg = <6>;
i2c-mux-idle-disconnect;
}; };
i2c@7 { i2c@7 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <7>; reg = <7>;
i2c-mux-idle-disconnect;
u41: pca9575@20 { u41: pca9575@20 {
compatible = "nxp,pca9575"; compatible = "nxp,pca9575";

2
arch/arm/boot/dts/am4372.dtsi
View File

@ -337,6 +337,8 @@
ti,hwmods = "dss_dispc"; ti,hwmods = "dss_dispc";
clocks = <&disp_clk>; clocks = <&disp_clk>;
clock-names = "fck"; clock-names = "fck";
max-memory-bandwidth = <230000000>;
}; };
rfbi: rfbi@4832a800 { rfbi: rfbi@4832a800 {

48
arch/arm/boot/dts/dra7-l4.dtsi
View File

@ -2732,7 +2732,7 @@
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr"; clock-names = "fck", "ahclkx", "ahclkr";
@ -2768,8 +2768,8 @@
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr"; clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled"; status = "disabled";
@ -2786,9 +2786,8 @@
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x68000 0x2000>, ranges = <0x0 0x68000 0x2000>,
@ -2804,7 +2803,7 @@
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
@ -2821,9 +2820,8 @@
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x6c000 0x2000>, ranges = <0x0 0x6c000 0x2000>,
@ -2839,7 +2837,7 @@
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
@ -2856,9 +2854,8 @@
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x70000 0x2000>, ranges = <0x0 0x70000 0x2000>,
@ -2874,7 +2871,7 @@
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
@ -2891,9 +2888,8 @@
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x74000 0x2000>, ranges = <0x0 0x74000 0x2000>,
@ -2909,7 +2905,7 @@
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
@ -2926,9 +2922,8 @@
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x78000 0x2000>, ranges = <0x0 0x78000 0x2000>,
@ -2944,7 +2939,7 @@
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
@ -2961,9 +2956,8 @@
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x7c000 0x2000>, ranges = <0x0 0x7c000 0x2000>,
@ -2979,7 +2973,7 @@
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";

4
arch/arm/boot/dts/logicpd-torpedo-som.dtsi
View File

@ -192,3 +192,7 @@
&twl_gpio { &twl_gpio {
ti,use-leds; ti,use-leds;
}; };
&twl_keypad {
status = "disabled";
};

1
arch/arm/boot/dts/omap3-gta04.dtsi
View File

@ -124,6 +124,7 @@
spi-max-frequency = <100000>; spi-max-frequency = <100000>;
spi-cpol; spi-cpol;
spi-cpha; spi-cpha;
spi-cs-high;
backlight= <&backlight>; backlight= <&backlight>;
label = "lcd"; label = "lcd";

2
arch/arm/boot/dts/omap4-droid4-xt894.dts
View File

@ -369,7 +369,7 @@
compatible = "ti,wl1285", "ti,wl1283"; compatible = "ti,wl1285", "ti,wl1283";
reg = <2>; reg = <2>;
/* gpio_100 with gpmc_wait2 pad as wakeirq */ /* gpio_100 with gpmc_wait2 pad as wakeirq */
interrupts-extended = <&gpio4 4 IRQ_TYPE_EDGE_RISING>, interrupts-extended = <&gpio4 4 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x4e>; <&omap4_pmx_core 0x4e>;
interrupt-names = "irq", "wakeup"; interrupt-names = "irq", "wakeup";
ref-clock-frequency = <26000000>; ref-clock-frequency = <26000000>;

2
arch/arm/boot/dts/omap4-panda-common.dtsi
View File

@ -474,7 +474,7 @@
compatible = "ti,wl1271"; compatible = "ti,wl1271";
reg = <2>; reg = <2>;
/* gpio_53 with gpmc_ncs3 pad as wakeup */ /* gpio_53 with gpmc_ncs3 pad as wakeup */
interrupts-extended = <&gpio2 21 IRQ_TYPE_EDGE_RISING>, interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x3a>; <&omap4_pmx_core 0x3a>;
interrupt-names = "irq", "wakeup"; interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>; ref-clock-frequency = <38400000>;

2
arch/arm/boot/dts/omap4-sdp.dts
View File

@ -512,7 +512,7 @@
compatible = "ti,wl1281"; compatible = "ti,wl1281";
reg = <2>; reg = <2>;
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_EDGE_RISING>; /* gpio 53 */ interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
ref-clock-frequency = <26000000>; ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>; tcxo-clock-frequency = <26000000>;
}; };

2
arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
View File

@ -69,7 +69,7 @@
compatible = "ti,wl1271"; compatible = "ti,wl1271";
reg = <2>; reg = <2>;
interrupt-parent = <&gpio2>; interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_EDGE_RISING>; /* gpio 41 */ interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; /* gpio 41 */
ref-clock-frequency = <38400000>; ref-clock-frequency = <38400000>;
}; };
}; };

2
arch/arm/boot/dts/omap5-board-common.dtsi
View File

@ -362,7 +362,7 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&wlcore_irq_pin>; pinctrl-0 = <&wlcore_irq_pin>;
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_EDGE_RISING>; /* gpio 14 */ interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
ref-clock-frequency = <26000000>; ref-clock-frequency = <26000000>;
}; };
}; };

2
arch/arm/boot/dts/omap54xx-clocks.dtsi
View File

@ -1146,7 +1146,7 @@
}; };
}; };
gpu_cm: clock-controller@1500 { gpu_cm: gpu_cm@1500 {
compatible = "ti,omap4-cm"; compatible = "ti,omap4-cm";
reg = <0x1500 0x100>; reg = <0x1500 0x100>;
#address-cells = <1>; #address-cells = <1>;

15
arch/arm/configs/omap2plus_defconfig
View File

@ -356,14 +356,15 @@ CONFIG_DRM_OMAP_CONNECTOR_HDMI=m
CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m CONFIG_DRM_OMAP_CONNECTOR_ANALOG_TV=m
CONFIG_DRM_OMAP_PANEL_DPI=m CONFIG_DRM_OMAP_PANEL_DPI=m
CONFIG_DRM_OMAP_PANEL_DSI_CM=m CONFIG_DRM_OMAP_PANEL_DSI_CM=m
CONFIG_DRM_OMAP_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_OMAP_PANEL_LGPHILIPS_LB035Q02=m
CONFIG_DRM_OMAP_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_OMAP_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_TILCDC=m CONFIG_DRM_TILCDC=m
CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_TI_TFP410=m
CONFIG_DRM_PANEL_LG_LB035Q02=m
CONFIG_DRM_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_PANEL_SHARP_LS037V7DW01=m
CONFIG_DRM_PANEL_SONY_ACX565AKM=m
CONFIG_DRM_PANEL_TPO_TD028TTEC1=m
CONFIG_DRM_PANEL_TPO_TD043MTEA1=m
CONFIG_FB=y CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MODE_HELPERS=y
@ -423,6 +424,7 @@ CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_TEST=m CONFIG_USB_TEST=m
CONFIG_NOP_USB_XCEIV=m CONFIG_NOP_USB_XCEIV=m
CONFIG_AM335X_PHY_USB=m CONFIG_AM335X_PHY_USB=m
@ -460,6 +462,7 @@ CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m CONFIG_LEDS_CLASS=m
CONFIG_LEDS_CPCAP=m CONFIG_LEDS_CPCAP=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_GPIO=m CONFIG_LEDS_GPIO=m
CONFIG_LEDS_PCA963X=m CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_PWM=m CONFIG_LEDS_PWM=m

5
arch/arm/mach-omap2/Makefile
View File

@ -29,6 +29,11 @@ obj-y += mcbsp.o
endif endif
obj-$(CONFIG_TWL4030_CORE) += omap_twl.o obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
ifneq ($(CONFIG_MFD_CPCAP),)
obj-y += pmic-cpcap.o
endif
obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
# SMP support ONLY available for OMAP4 # SMP support ONLY available for OMAP4

1
arch/arm/mach-omap2/control.h
View File

@ -195,6 +195,7 @@
#define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243 #define OMAP44XX_CONTROL_FUSE_MPU_OPP100 0x243
#define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246 #define OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO 0x246
#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249 #define OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO 0x249
#define OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB 0x24C
#define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254 #define OMAP44XX_CONTROL_FUSE_CORE_OPP50 0x254
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257 #define OMAP44XX_CONTROL_FUSE_CORE_OPP100 0x257
#define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A #define OMAP44XX_CONTROL_FUSE_CORE_OPP100OV 0x25A

2
arch/arm/mach-omap2/omap-mpuss-lowpower.c
View File

@ -227,7 +227,6 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
{ {
struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu); struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET; unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
unsigned int wakeup_cpu;
if (omap_rev() == OMAP4430_REV_ES1_0) if (omap_rev() == OMAP4430_REV_ES1_0)
return -ENXIO; return -ENXIO;
@ -292,7 +291,6 @@ int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
* secure devices, CPUx does WFI which can result in * secure devices, CPUx does WFI which can result in
* domain transition * domain transition
*/ */
wakeup_cpu = smp_processor_id();
pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON); pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
pwrdm_post_transition(NULL); pwrdm_post_transition(NULL);

3
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
View File

@ -763,7 +763,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
.rev_offs = 0x0000, .rev_offs = 0x0000,
.sysc_offs = 0x0010, .sysc_offs = 0x0010,
.syss_offs = 0x0014, .syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_RESET_STATUS,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP), SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2,

5
arch/arm/mach-omap2/omap_hwmod_33xx_data.c
View File

@ -231,8 +231,9 @@ static struct omap_hwmod am33xx_control_hwmod = {
static struct omap_hwmod_class_sysconfig lcdc_sysc = { static struct omap_hwmod_class_sysconfig lcdc_sysc = {
.rev_offs = 0x0, .rev_offs = 0x0,
.sysc_offs = 0x54, .sysc_offs = 0x54,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
.sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2,
}; };

8
arch/arm/mach-omap2/omap_twl.c
View File

@ -36,11 +36,6 @@
#define OMAP4_VDD_CORE_SR_VOLT_REG 0x61 #define OMAP4_VDD_CORE_SR_VOLT_REG 0x61
#define OMAP4_VDD_CORE_SR_CMD_REG 0x62 #define OMAP4_VDD_CORE_SR_CMD_REG 0x62
#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
static bool is_offset_valid; static bool is_offset_valid;
static u8 smps_offset; static u8 smps_offset;
@ -219,7 +214,8 @@ int __init omap4_twl_init(void)
{ {
struct voltagedomain *voltdm; struct voltagedomain *voltdm;
if (!cpu_is_omap44xx()) if (!cpu_is_omap44xx() ||
of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
return -ENODEV; return -ENODEV;
voltdm = voltdm_lookup("mpu"); voltdm = voltdm_lookup("mpu");

16
arch/arm/mach-omap2/opp4xxx_data.c
View File

@ -32,20 +32,22 @@
#define OMAP4430_VDD_MPU_OPP50_UV 1025000 #define OMAP4430_VDD_MPU_OPP50_UV 1025000
#define OMAP4430_VDD_MPU_OPP100_UV 1200000 #define OMAP4430_VDD_MPU_OPP100_UV 1200000
#define OMAP4430_VDD_MPU_OPPTURBO_UV 1313000 #define OMAP4430_VDD_MPU_OPPTURBO_UV 1325000
#define OMAP4430_VDD_MPU_OPPNITRO_UV 1375000 #define OMAP4430_VDD_MPU_OPPNITRO_UV 1388000
#define OMAP4430_VDD_MPU_OPPNITROSB_UV 1398000
struct omap_volt_data omap443x_vdd_mpu_volt_data[] = { struct omap_volt_data omap443x_vdd_mpu_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c), VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP50_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP50, 0xf4, 0x0c),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16), VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPP100_UV, OMAP44XX_CONTROL_FUSE_MPU_OPP100, 0xf9, 0x16),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23), VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPTURBO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPTURBO, 0xfa, 0x23),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27), VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITRO_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITRO, 0xfa, 0x27),
VOLT_DATA_DEFINE(OMAP4430_VDD_MPU_OPPNITROSB_UV, OMAP44XX_CONTROL_FUSE_MPU_OPPNITROSB, 0xfa, 0x27),
VOLT_DATA_DEFINE(0, 0, 0, 0), VOLT_DATA_DEFINE(0, 0, 0, 0),
}; };
#define OMAP4430_VDD_IVA_OPP50_UV 1013000 #define OMAP4430_VDD_IVA_OPP50_UV 950000
#define OMAP4430_VDD_IVA_OPP100_UV 1188000 #define OMAP4430_VDD_IVA_OPP100_UV 1114000
#define OMAP4430_VDD_IVA_OPPTURBO_UV 1300000 #define OMAP4430_VDD_IVA_OPPTURBO_UV 1291000
struct omap_volt_data omap443x_vdd_iva_volt_data[] = { struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c), VOLT_DATA_DEFINE(OMAP4430_VDD_IVA_OPP50_UV, OMAP44XX_CONTROL_FUSE_IVA_OPP50, 0xf4, 0x0c),
@ -54,8 +56,8 @@ struct omap_volt_data omap443x_vdd_iva_volt_data[] = {
VOLT_DATA_DEFINE(0, 0, 0, 0), VOLT_DATA_DEFINE(0, 0, 0, 0),
}; };
#define OMAP4430_VDD_CORE_OPP50_UV 1025000 #define OMAP4430_VDD_CORE_OPP50_UV 962000
#define OMAP4430_VDD_CORE_OPP100_UV 1200000 #define OMAP4430_VDD_CORE_OPP100_UV 1127000
struct omap_volt_data omap443x_vdd_core_volt_data[] = { struct omap_volt_data omap443x_vdd_core_volt_data[] = {
VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c), VOLT_DATA_DEFINE(OMAP4430_VDD_CORE_OPP50_UV, OMAP44XX_CONTROL_FUSE_CORE_OPP50, 0xf4, 0x0c),

101
arch/arm/mach-omap2/pm.c
View File

@ -74,83 +74,6 @@ int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
return 0; return 0;
} }
/*
* This API is to be called during init to set the various voltage
* domains to the voltage as per the opp table. Typically we boot up
* at the nominal voltage. So this function finds out the rate of
* the clock associated with the voltage domain, finds out the correct
* opp entry and sets the voltage domain to the voltage specified
* in the opp entry
*/
static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
const char *oh_name)
{
struct voltagedomain *voltdm;
struct clk *clk;
struct dev_pm_opp *opp;
unsigned long freq, bootup_volt;
struct device *dev;
if (!vdd_name || !clk_name || !oh_name) {
pr_err("%s: invalid parameters\n", __func__);
goto exit;
}
if (!strncmp(oh_name, "mpu", 3))
/*
* All current OMAPs share voltage rail and clock
* source, so CPU0 is used to represent the MPU-SS.
*/
dev = get_cpu_device(0);
else
dev = omap_device_get_by_hwmod_name(oh_name);
if (IS_ERR(dev)) {
pr_err("%s: Unable to get dev pointer for hwmod %s\n",
__func__, oh_name);
goto exit;
}
voltdm = voltdm_lookup(vdd_name);
if (!voltdm) {
pr_err("%s: unable to get vdd pointer for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
clk = clk_get(NULL, clk_name);
if (IS_ERR(clk)) {
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
goto exit;
}
freq = clk_get_rate(clk);
clk_put(clk);
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
if (IS_ERR(opp)) {
pr_err("%s: unable to find boot up OPP for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
bootup_volt = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
if (!bootup_volt) {
pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
voltdm_scale(voltdm, bootup_volt);
return 0;
exit:
pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
return -EINVAL;
}
#ifdef CONFIG_SUSPEND #ifdef CONFIG_SUSPEND
static int omap_pm_enter(suspend_state_t suspend_state) static int omap_pm_enter(suspend_state_t suspend_state)
{ {
@ -208,25 +131,6 @@ void omap_common_suspend_init(void *pm_suspend)
} }
#endif /* CONFIG_SUSPEND */ #endif /* CONFIG_SUSPEND */
static void __init omap3_init_voltages(void)
{
if (!soc_is_omap34xx())
return;
omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
omap2_set_init_voltage("core", "l3_ick", "l3_main");
}
static void __init omap4_init_voltages(void)
{
if (!soc_is_omap44xx())
return;
omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
}
int __maybe_unused omap_pm_nop_init(void) int __maybe_unused omap_pm_nop_init(void)
{ {
return 0; return 0;
@ -244,12 +148,9 @@ int __init omap2_common_pm_late_init(void)
/* Init the voltage layer */ /* Init the voltage layer */
omap3_twl_init(); omap3_twl_init();
omap4_twl_init(); omap4_twl_init();
omap4_cpcap_init();
omap_voltage_late_init(); omap_voltage_late_init();
/* Initialize the voltages */
omap3_init_voltages();
omap4_init_voltages();
/* Smartreflex device init */ /* Smartreflex device init */
omap_devinit_smartreflex(); omap_devinit_smartreflex();

14
arch/arm/mach-omap2/pm.h
View File

@ -107,6 +107,11 @@ extern u16 pm44xx_errata;
#define IS_PM44XX_ERRATUM(id) 0 #define IS_PM44XX_ERRATUM(id) 0
#endif #endif
#define OMAP4_VP_CONFIG_ERROROFFSET 0x00
#define OMAP4_VP_VSTEPMIN_VSTEPMIN 0x01
#define OMAP4_VP_VSTEPMAX_VSTEPMAX 0x04
#define OMAP4_VP_VLIMITTO_TIMEOUT_US 200
#ifdef CONFIG_POWER_AVS_OMAP #ifdef CONFIG_POWER_AVS_OMAP
extern int omap_devinit_smartreflex(void); extern int omap_devinit_smartreflex(void);
extern void omap_enable_smartreflex_on_init(void); extern void omap_enable_smartreflex_on_init(void);
@ -134,6 +139,15 @@ static inline int omap4_twl_init(void)
} }
#endif #endif
#if IS_ENABLED(CONFIG_MFD_CPCAP)
extern int omap4_cpcap_init(void);
#else
static inline int omap4_cpcap_init(void)
{
return -EINVAL;
}
#endif
#ifdef CONFIG_PM #ifdef CONFIG_PM
extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut); extern void omap_pm_setup_oscillator(u32 tstart, u32 tshut);
extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut); extern void omap_pm_get_oscillator(u32 *tstart, u32 *tshut);

13
arch/arm/mach-omap2/pm44xx.c
View File

@ -128,18 +128,9 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
return 0; return 0;
} }
/*
* Bootloader or kexec boot may have LOGICRETSTATE cleared
* for some domains. This is the case when kexec booting from
* Android kernels that support off mode for example.
* Make sure it's set at least for core and per, otherwise
* we currently will see lost GPIO interrupts for wlcore and
* smsc911x at least if per hits retention during idle.
*/
if (!strncmp(pwrdm->name, "core", 4) || if (!strncmp(pwrdm->name, "core", 4) ||
!strncmp(pwrdm->name, "l4per", 5) || !strncmp(pwrdm->name, "l4per", 5))
!strncmp(pwrdm->name, "wkup", 4)) pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_OFF);
pwrdm_set_logic_retst(pwrdm, PWRDM_POWER_RET);
pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC); pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
if (!pwrst) if (!pwrst)

271
arch/arm/mach-omap2/pmic-cpcap.c Normal file
View File

@ -0,0 +1,271 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* pmic-cpcap.c - CPCAP-specific functions for the OPP code
*
* Adapted from Motorola Mapphone Android Linux kernel
* Copyright (C) 2011 Motorola, Inc.
*/
#include <linux/err.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include "soc.h"
#include "pm.h"
#include "voltage.h"
#include <linux/init.h>
#include "vc.h"
/**
* omap_cpcap_vsel_to_vdc - convert CPCAP VSEL value to microvolts DC
* @vsel: CPCAP VSEL value to convert
*
* Returns the microvolts DC that the CPCAP PMIC should generate when
* programmed with @vsel.
*/
static unsigned long omap_cpcap_vsel_to_uv(unsigned char vsel)
{
if (vsel > 0x44)
vsel = 0x44;
return (((vsel * 125) + 6000)) * 100;
}
/**
* omap_cpcap_uv_to_vsel - convert microvolts DC to CPCAP VSEL value
* @uv: microvolts DC to convert
*
* Returns the VSEL value necessary for the CPCAP PMIC to
* generate an output voltage equal to or greater than @uv microvolts DC.
*/
static unsigned char omap_cpcap_uv_to_vsel(unsigned long uv)
{
if (uv < 600000)
uv = 600000;
else if (uv > 1450000)
uv = 1450000;
return DIV_ROUND_UP(uv - 600000, 12500);
}
static struct omap_voltdm_pmic omap_cpcap_core = {
.slew_rate = 4000,
.step_size = 12500,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 900000,
.vddmax = 1350000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x02,
.volt_reg_addr = 0x00,
.cmd_reg_addr = 0x01,
.i2c_high_speed = false,
.vsel_to_uv = omap_cpcap_vsel_to_uv,
.uv_to_vsel = omap_cpcap_uv_to_vsel,
};
static struct omap_voltdm_pmic omap_cpcap_iva = {
.slew_rate = 4000,
.step_size = 12500,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 900000,
.vddmax = 1350000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x44,
.volt_reg_addr = 0x0,
.cmd_reg_addr = 0x01,
.i2c_high_speed = false,
.vsel_to_uv = omap_cpcap_vsel_to_uv,
.uv_to_vsel = omap_cpcap_uv_to_vsel,
};
/**
* omap_max8952_vsel_to_vdc - convert MAX8952 VSEL value to microvolts DC
* @vsel: MAX8952 VSEL value to convert
*
* Returns the microvolts DC that the MAX8952 Regulator should generate when
* programmed with @vsel.
*/
static unsigned long omap_max8952_vsel_to_uv(unsigned char vsel)
{
if (vsel > 0x3F)
vsel = 0x3F;
return (((vsel * 100) + 7700)) * 100;
}
/**
* omap_max8952_uv_to_vsel - convert microvolts DC to MAX8952 VSEL value
* @uv: microvolts DC to convert
*
* Returns the VSEL value necessary for the MAX8952 Regulator to
* generate an output voltage equal to or greater than @uv microvolts DC.
*/
static unsigned char omap_max8952_uv_to_vsel(unsigned long uv)
{
if (uv < 770000)
uv = 770000;
else if (uv > 1400000)
uv = 1400000;
return DIV_ROUND_UP(uv - 770000, 10000);
}
static struct omap_voltdm_pmic omap443x_max8952_mpu = {
.slew_rate = 16000,
.step_size = 10000,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 900000,
.vddmax = 1400000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x60,
.volt_reg_addr = 0x03,
.cmd_reg_addr = 0x03,
.i2c_high_speed = false,
.vsel_to_uv = omap_max8952_vsel_to_uv,
.uv_to_vsel = omap_max8952_uv_to_vsel,
};
/**
* omap_fan5355_vsel_to_vdc - convert FAN535503 VSEL value to microvolts DC
* @vsel: FAN535503 VSEL value to convert
*
* Returns the microvolts DC that the FAN535503 Regulator should generate when
* programmed with @vsel.
*/
static unsigned long omap_fan535503_vsel_to_uv(unsigned char vsel)
{
/* Extract bits[5:0] */
vsel &= 0x3F;
return (((vsel * 125) + 7500)) * 100;
}
/**
* omap_fan535508_vsel_to_vdc - convert FAN535508 VSEL value to microvolts DC
* @vsel: FAN535508 VSEL value to convert
*
* Returns the microvolts DC that the FAN535508 Regulator should generate when
* programmed with @vsel.
*/
static unsigned long omap_fan535508_vsel_to_uv(unsigned char vsel)
{
/* Extract bits[5:0] */
vsel &= 0x3F;
if (vsel > 0x37)
vsel = 0x37;
return (((vsel * 125) + 7500)) * 100;
}
/**
* omap_fan535503_uv_to_vsel - convert microvolts DC to FAN535503 VSEL value
* @uv: microvolts DC to convert
*
* Returns the VSEL value necessary for the MAX8952 Regulator to
* generate an output voltage equal to or greater than @uv microvolts DC.
*/
static unsigned char omap_fan535503_uv_to_vsel(unsigned long uv)
{
unsigned char vsel;
if (uv < 750000)
uv = 750000;
else if (uv > 1537500)
uv = 1537500;
vsel = DIV_ROUND_UP(uv - 750000, 12500);
return vsel | 0xC0;
}
/**
* omap_fan535508_uv_to_vsel - convert microvolts DC to FAN535508 VSEL value
* @uv: microvolts DC to convert
*
* Returns the VSEL value necessary for the MAX8952 Regulator to
* generate an output voltage equal to or greater than @uv microvolts DC.
*/
static unsigned char omap_fan535508_uv_to_vsel(unsigned long uv)
{
unsigned char vsel;
if (uv < 750000)
uv = 750000;
else if (uv > 1437500)
uv = 1437500;
vsel = DIV_ROUND_UP(uv - 750000, 12500);
return vsel | 0xC0;
}
/* fan5335-core */
static struct omap_voltdm_pmic omap4_fan_core = {
.slew_rate = 4000,
.step_size = 12500,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 850000,
.vddmax = 1375000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x4A,
.i2c_high_speed = false,
.volt_reg_addr = 0x01,
.cmd_reg_addr = 0x01,
.vsel_to_uv = omap_fan535508_vsel_to_uv,
.uv_to_vsel = omap_fan535508_uv_to_vsel,
};
/* fan5335 iva */
static struct omap_voltdm_pmic omap4_fan_iva = {
.slew_rate = 4000,
.step_size = 12500,
.vp_erroroffset = OMAP4_VP_CONFIG_ERROROFFSET,
.vp_vstepmin = OMAP4_VP_VSTEPMIN_VSTEPMIN,
.vp_vstepmax = OMAP4_VP_VSTEPMAX_VSTEPMAX,
.vddmin = 850000,
.vddmax = 1375000,
.vp_timeout_us = OMAP4_VP_VLIMITTO_TIMEOUT_US,
.i2c_slave_addr = 0x48,
.volt_reg_addr = 0x01,
.cmd_reg_addr = 0x01,
.i2c_high_speed = false,
.vsel_to_uv = omap_fan535503_vsel_to_uv,
.uv_to_vsel = omap_fan535503_uv_to_vsel,
};
int __init omap4_cpcap_init(void)
{
struct voltagedomain *voltdm;
if (!of_find_compatible_node(NULL, NULL, "motorola,cpcap"))
return -ENODEV;
voltdm = voltdm_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap443x_max8952_mpu);
if (of_machine_is_compatible("motorola,droid-bionic")) {
voltdm = voltdm_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap_cpcap_core);
voltdm = voltdm_lookup("mpu");
omap_voltage_register_pmic(voltdm, &omap_cpcap_iva);
} else {
voltdm = voltdm_lookup("core");
omap_voltage_register_pmic(voltdm, &omap4_fan_core);
voltdm = voltdm_lookup("iva");
omap_voltage_register_pmic(voltdm, &omap4_fan_iva);
}
return 0;
}
static int __init cpcap_late_init(void)
{
omap4_vc_set_pmic_signaling(PWRDM_POWER_RET);
return 0;
}
omap_late_initcall(cpcap_late_init);

57
arch/arm/mach-omap2/vc.c
View File

@ -26,6 +26,31 @@
#include "scrm44xx.h" #include "scrm44xx.h"
#include "control.h" #include "control.h"
#define OMAP4430_VDD_IVA_I2C_DISABLE BIT(14)
#define OMAP4430_VDD_MPU_I2C_DISABLE BIT(13)
#define OMAP4430_VDD_CORE_I2C_DISABLE BIT(12)
#define OMAP4430_VDD_IVA_PRESENCE BIT(9)
#define OMAP4430_VDD_MPU_PRESENCE BIT(8)
#define OMAP4430_AUTO_CTRL_VDD_IVA(x) ((x) << 4)
#define OMAP4430_AUTO_CTRL_VDD_MPU(x) ((x) << 2)
#define OMAP4430_AUTO_CTRL_VDD_CORE(x) ((x) << 0)
#define OMAP4430_AUTO_CTRL_VDD_RET 2
#define OMAP4430_VDD_I2C_DISABLE_MASK \
(OMAP4430_VDD_IVA_I2C_DISABLE | \
OMAP4430_VDD_MPU_I2C_DISABLE | \
OMAP4430_VDD_CORE_I2C_DISABLE)
#define OMAP4_VDD_DEFAULT_VAL \
(OMAP4430_VDD_I2C_DISABLE_MASK | \
OMAP4430_VDD_IVA_PRESENCE | OMAP4430_VDD_MPU_PRESENCE | \
OMAP4430_AUTO_CTRL_VDD_IVA(OMAP4430_AUTO_CTRL_VDD_RET) | \
OMAP4430_AUTO_CTRL_VDD_MPU(OMAP4430_AUTO_CTRL_VDD_RET) | \
OMAP4430_AUTO_CTRL_VDD_CORE(OMAP4430_AUTO_CTRL_VDD_RET))
#define OMAP4_VDD_RET_VAL \
(OMAP4_VDD_DEFAULT_VAL & ~OMAP4430_VDD_I2C_DISABLE_MASK)
/** /**
* struct omap_vc_channel_cfg - describe the cfg_channel bitfield * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
* @sa: bit for slave address * @sa: bit for slave address
@ -280,6 +305,26 @@ void omap3_vc_set_pmic_signaling(int core_next_state)
} }
} }
void omap4_vc_set_pmic_signaling(int core_next_state)
{
struct voltagedomain *vd = vc.vd;
u32 val;
if (!vd)
return;
switch (core_next_state) {
case PWRDM_POWER_RET:
val = OMAP4_VDD_RET_VAL;
break;
default:
val = OMAP4_VDD_DEFAULT_VAL;
break;
}
vd->write(val, OMAP4_PRM_VOLTCTRL_OFFSET);
}
/* /*
* Configure signal polarity for sys_clkreq and sys_off_mode pins * Configure signal polarity for sys_clkreq and sys_off_mode pins
* as the default values are wrong and can cause the system to hang * as the default values are wrong and can cause the system to hang
@ -542,9 +587,19 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME); writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
} }
static void __init omap4_vc_init_pmic_signaling(struct voltagedomain *voltdm)
{
if (vc.vd)
return;
vc.vd = voltdm;
voltdm->write(OMAP4_VDD_DEFAULT_VAL, OMAP4_PRM_VOLTCTRL_OFFSET);
}
/* OMAP4 specific voltage init functions */ /* OMAP4 specific voltage init functions */
static void __init omap4_vc_init_channel(struct voltagedomain *voltdm) static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
{ {
omap4_vc_init_pmic_signaling(voltdm);
omap4_set_timings(voltdm, true); omap4_set_timings(voltdm, true);
omap4_set_timings(voltdm, false); omap4_set_timings(voltdm, false);
} }
@ -615,7 +670,7 @@ static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
const struct i2c_init_data *i2c_data; const struct i2c_init_data *i2c_data;
if (!voltdm->pmic->i2c_high_speed) { if (!voltdm->pmic->i2c_high_speed) {
pr_warn("%s: only high speed supported!\n", __func__); pr_info("%s: using bootloader low-speed timings\n", __func__);
return; return;
} }

2
arch/arm/mach-omap2/vc.h
View File

@ -117,7 +117,7 @@ extern struct omap_vc_param omap4_iva_vc_data;
extern struct omap_vc_param omap4_core_vc_data; extern struct omap_vc_param omap4_core_vc_data;
void omap3_vc_set_pmic_signaling(int core_next_state); void omap3_vc_set_pmic_signaling(int core_next_state);
void omap4_vc_set_pmic_signaling(int core_next_state);
void omap_vc_init_channel(struct voltagedomain *voltdm); void omap_vc_init_channel(struct voltagedomain *voltdm);
int omap_vc_pre_scale(struct voltagedomain *voltdm, int omap_vc_pre_scale(struct voltagedomain *voltdm,

6
drivers/clk/ti/clk-7xx.c
View File

@ -683,7 +683,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" }, { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" }, { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" }, { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" }, { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" }, { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" }, { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" }, { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
@ -828,8 +828,8 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"), DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"), DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"), DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"), DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"), DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"), DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"), DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),