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powerpc: Use 32 bit loads and stores when operating on condition register values 

The condition register (CR) is a 32 bit quantity so we should use
32 bit loads and stores.

Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Anton Blanchard 2013-10-15 14:36:31 +11:00 committed by Benjamin Herrenschmidt
parent 65508689d4
commit bbe30b3b57
2 changed files with 6 additions and 6 deletions
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8
arch/powerpc/kernel/tm.S
View File

@ -106,7 +106,7 @@ DSCR_DEFAULT:
_GLOBAL(tm_reclaim)
mfcr r6
mflr r0
std r6, 8(r1)
stw r6, 8(r1)
std r0, 16(r1)
std r2, 40(r1)
stdu r1, -TM_FRAME_SIZE(r1)
@ -285,7 +285,7 @@ dont_backup_fp:
REST_NVGPRS(r1)
addi r1, r1, TM_FRAME_SIZE
ld r4, 8(r1)
lwz r4, 8(r1)
ld r0, 16(r1)
mtcr r4
mtlr r0
@ -310,7 +310,7 @@ dont_backup_fp:
_GLOBAL(tm_recheckpoint)
mfcr r5
mflr r0
std r5, 8(r1)
stw r5, 8(r1)
std r0, 16(r1)
std r2, 40(r1)
stdu r1, -TM_FRAME_SIZE(r1)
@ -444,7 +444,7 @@ restore_gprs:
REST_NVGPRS(r1)
addi r1, r1, TM_FRAME_SIZE
ld r4, 8(r1)
lwz r4, 8(r1)
ld r0, 16(r1)
mtcr r4
mtlr r0

4
arch/powerpc/platforms/powernv/opal-wrappers.S
View File

@ -24,7 +24,7 @@
mflr r0; \
mfcr r12; \
std r0,16(r1); \
std r12,8(r1); \
stw r12,8(r1); \
std r1,PACAR1(r13); \
li r0,0; \
mfmsr r12; \
@ -53,7 +53,7 @@ _STATIC(opal_return)
*/
FIXUP_ENDIAN
ld r2,PACATOC(r13);
ld r4,8(r1);
lwz r4,8(r1);
ld r5,16(r1);
ld r6,PACASAVEDMSR(r13);
mtspr SPRN_SRR0,r5;